Patent Application
20080176358
1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor package, and more particularly to a fabrication method of a multichip stacking structure.
2. Description of the Prior Art
Due to development of the electronic industry, techniques relating to miniaturization and high operational speed for electronic devices are desirable. In such demand, semiconductor packages have evolved gradually to increase the electrical functionality and capability in a single semiconductor package, and multichip module has become a popular trend to be adopted in the fabrication of semiconductor packages. Multichip module is a technology to assemble two or more semiconductor chips in a single package, so as to reduce the overall size of the circuit structure in an electronic product, and to improve electrical functionality. In other words, with the capability to assemble two or more chips in a single semiconductor package, the multichip structures effectively increase the system operational speed. Moreover, multichip structures can reduce the connection length between each chip so as to reduce the signal delay and to save time.
A side-by-side method is commonly adopted by the multichip structure, in which more than two chips are disposed side-by-side on a main mounting surface of a carrier. The electrical connection between such chips and circuits on the carrier is established through a wire bonding method. However, as the number of the chips in such side-by-side multichip module increase, the main mounting surface of the carrier is increased accordingly, which further results in the undesirable high packaging cost and relatively large package size.
In order to solve the foregoing drawbacks of the prior art, in recent years an upright stacking technique is adopted to stack chips, and the stacking of chips has some variation according to the design of the chip and the wire bonding process. However, if the chips are designed to have bond pads concentrated on one side, such as flash memory chips, a step-like stacking must be performed for the convenience of wire bondings. For example, as shown in
Such multichip stacking structure can reduce the required mounting area in comparison with side-by-side method, and is also advantageous for performing chip stacking before wire bonding. However, due to such stacking technique deposing the chips deviated from the previous one towards one direction, such staking structure is disadvantageous in that the projection area of the whole stacking chip module is enlarged as the number of the stacking chips is increased. As shown in
Please refer to
However, such multichip stacking structure still possesses a few drawbacks. First, an extra process for deposing the buffering element is required for stacking chips, thereby increasing the fabrication cost and fabricating steps. Moreover, due to the deposition of the buffering layer, the height of such multichip stacking structure cannot be effectively reduced, which is unfavorable to the fabrication of low-profile electronic device (such as Micro-SD card).
Thus, there is an urgent need to develop a multichip stacking structure, which allows multiple chips to be packaged within a single package without additionally increasing the package area and height for low-profile electronic products and also gives good considerations for reducing processing steps and fabrication cost.
In light of the foregoing drawbacks of the prior art, a primary objective of the present invention is to provide a fabrication method of a multichip stacking structure for stacking multiple chips without additional increasing package area and height.
Another objective of the present invention is to provide a fabrication method of a multichip stacking structure for a low-profile electronic device.
Yet another objective of the present invention is to provide a fabrication method of a semiconductor package structure with reduced fabricating cost and steps in chip stacking.
In order to achieve the foregoing and other objectives, the present invention provides a fabrication method of a semiconductor package structure. The fabrication method comprises the steps of: preparing a chip carrier and a plurality of first and second chips, wherein each chip has a bond pad disposed at an edge of a surface thereof; stacking the first chips on the chip carrier to form a first chip module, the first chips are stacked in a step-like manner in a first direction away from the bond pads of the first chip to expose the bond pads of the first chips; electrically connecting the bond pads of the first chips to the chip carrier by a plurality of first bonding wires; stacking the second chips on the first chip module to form a second chip module, wherein the second chips are stacked in the step-like manner to expose the bond pads of the second chips, a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer with the bottom chip deviated from the top chip horizontally in a second direction toward the first bonding wires of the first chips, and a plurality of fillers are disposed within the adhesive layer for supporting the bottom chip; and electrically connecting the bond pads of the second chips to the chip carrier by a plurality of second bonding wires.
Another fabrication method of the multichip stacking structure of another embodiment of the invention is provided, wherein the method comprises the steps of: preparing a chip carrier and a plurality of first and second chips, wherein each chip has a bond pad disposed at an edge of a surface thereof; stacking the first chips on the chip carrier to form a first chip module, wherein the first chips are stacked in a step-like manner in a first direction away from the bond pads of the first chips to expose the bond pads of the first chips; electrically connecting the bond pads of the first chips to the chip carrier by a plurality of first bonding wires; stacking the second chips on the first chip module to form a second chip module, wherein the second chips are stacked in the step-like manner to expose the bond pads of the second chips, a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive film with the bottom chip deviated from the top chip horizontally in a second direction toward the first bonding wires of the first chips, and a portion of the first bonding wire of the top chip is covered by the adhesive film; and electrically connecting the bond pads of the second chips to the chip carrier by a plurality of second bonding wires.
After that, an encapsulant is deposed on the chip carrier for encapsulating the first and the second chip modules and the first and second bonding wires. Preferably, the projection of the second chip module is within (i.e. does not exceed) the projection of the first chip module. In addition, the first and second chip modules are electrically connected to the chip carrier by a general wire bonding method or reverse wire bond method, in which the reverse wire bond method allows an outer end of the bonding wire to be bonded to the chip carrier prior bonding an inner end of the bonding wire to the chip, so as to reduce the height of the wire loop, which further reduces the thickness of the adhesive layer or the adhesive film, thereby permitting a smaller and more light-weighted multichip stacking structure with more chips being stacked to be fabricated.
Each of the plurality of chips in the first and second chip modules with the bond pad thereof to be deposed on a single side of the respective modules. The chips are stacked in the mentioned step-like manner, which means that each upper one is shifted horizontally a predetermined distance in respective to the respective one therebeneath, i.e. away from the edges deposed with the bond pads. That is to say, the chips stacked in such way prevents the chip stacking from blocking a space vertically above the bond pads of the chip underneath, and favoring the wire bonding process to electrically connect the chips to the chip carrier by the plurality of bonding wires.
Furthermore, still another embodiment of the multichip stacking structure and the fabrication method thereof of the invention are provided. The fabrication method comprises steps of: stacking a first chip module on a chip carrier; electrically connecting the first chip module to the chip carrier by a plurality of first bonding wires; forming a second chip module consisting of at least one chip on the first chip module by mounting a non-conductive adhesive layer between the first and the second chip module; wherein a plurality of fillers are disposed within the adhesive layer for supporting the bottom chip of the second chip module; and electrically connecting the second chip module to the chip carrier by a plurality of second bonding wires, wherein the second chip module is corresponding to a top chip of the first chip module in position or deviated a predetermined distance from a top chip of the first chip module. Alternatively, the formation of the second chip module is performed by steps of: providing at least one chip with a non-conductive adhesive layer pre-adhered to a surface thereof; and pressing the at least one chip on the first chip module so as to allow a portion of the first bounding wire of a top chip of the first chip module to be covered by the adhesive film.
Thus, according to the multichip stacking structure of the invention, the multiple chips each having the bond pad disposed on one side are sequentially stacked on the chip carrier in a step-like manner to form a first chip module. Then a plurality of first bonding wires are used to electrically connect the first chip module to the chip carrier. The numbers of chips to be stacked can be up to the maximum that can be packaged on the carrier. Then, the bottom chip of the second chip module is deposed on the top chip of the first chip module by the adhesive layer having filters therein for support the bottom chip or the adhesive film for covering the portion of the first bonding wire between the bottom chip of the second chip module and the top chip of the first chip module in a way that the bottom chip is deviated from the top chip horizontally in a direction toward the first bonding wires of the first chip module. Then remaining chips for the second chip module are stacked on the bottom chip in a manner as the stacking process for stacking chips of the first chip module. In such way, the problem that all chips deposed towards one direction is prevented and as a result more chips can be stacked. Moreover, the additional costs and fabrication steps for the additional deposing of buffering element in the prior art can be also eliminated. The multiple stacking structure provided by the present invention thus provides a solution to perform multiple chip stacking free from increasing package area and height, and is suitable for a light-weighted, small and low profile electronic device.
The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
The present invention is described in the following with specific embodiments, so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the present invention.
Referring to
As shown in
As shown in
In the present embodiment, the first chip module 31 comprises the chips 311 and 312 (not limited to two chips), wherein the chips 311 and 312 are approximate in size with a side length thereof being S, and have the bond pads 311a, 312a on respective single sides thereof. The chip 312 is shifted a predetermined distance L away from the bond pad 311a of the chip 311, so that a space vertically above the bond pad 311a would not be blocked by the chip 312, which allows to perform the wire bonding process to electrically connect the chips 311 and 312 to the chip carrier 30 by the first bonding wires 341.
As shown in
Please refer to
In the embodiment, the second chip module 32 comprises the chips 323 and 324 (not limited to two chips), which have the bond pad 323a and a bond pad 324a respectively on respective single sides thereof. The chip 324 is horizontally shifted a predetermined distance L away from the bond pad 323a of the chip 323, so that the space vertically above the bond pad 323a would not be blocked by the chip 324, which allowing to perform the wire bonding process to electrically connect the chips 323 and 324 to the chip carrier 30 by the second bonding wires 342.
A preferable deposition position of the chip 323 of the second chip module 32 is a position that a projection of the chip 323 is corresponding to a position of the chip 311 of the first chip module 31. Similarly, a preferable deposition position of the chip 324 stacked on the chip 323 is a position that a projection of the chip 324 is corresponding to a position of the chip 312. In such way, regardless of how many stacking layers there are, the overall projection length of the stacking structure should remain as (S+L). Comparing with the increased projection length as a result of conventional step-like stacking with the chips shifted toward a single direction, the overall projected length of the stacking structure of the present embodiment of the invention is 2L less than the above-mentioned one in the prior art.
It should be noted that since the bottom chip (i.e. the chip 323) of the second chip module 32 is mounted on the top chip (i.e. the chip 312) in such a way that the chip 323 is deviated from the chip 312 horizontally in the direction toward the first bonding wires 341 of the first chip module 31, and the chip 324 is stacked on the chip 323 in a way as the stacking of the first chip module 31, the chips 311 and 312 and the chips 323 and 324 of the first and the second chip modules 31 and 32 respectively are not all stacked continuously toward a single direction. Hence, this embodiment prevents the package with mutichip from problems such as a large area of the chip carrier being occupied by the stacked chips and the stacking structure exceeding the maximal available size to be packaged. Moreover, since the chip 323 is mounted to the chip 312 by an adhesive layer 351 having fillers 350 filled therein, the present invention is also free from the problem in the prior art that a stacking height cannot be effectively reduced due to the use of buffering element. Preferably, the fillers 350 are made of insulation materials, or metal particles covered by an insulation film.
As shown in
Through the foregoing fabrication method, the multichip stacking structure disclosed in the present invention comprises: the chip carrier 30; the first chip module 31 having the plurality of first chips 311 and 312, wherein the first chips 311 and 312 respectively have bond pads 311a and 312a deposed at edges of surfaces thereof and the first chips 311 and 312 are stacked on the chip carrier 30 in a step-like manner to expose the bond pads 311a and 312a; the plurality of first bonding wires 341 for electrically connecting the bond pads 311a and 312a to the chip carrier 30; the second chip module 32 having the plurality of second chips 323 and 324, wherein the second chips 323 and 324 respectively have bond pads 323a and 324a deposed at edges of surface thereof, and the second chips 323 and 324 are stacked on the first chip module 31 to expose the bond pads 323a and 324a, the bottom chip (i.e. the chip 323) of the second chip module 32 is stacked on the top chip (i.e. the chip 312) of the first chip module 31 by the adhesive layer 351 having fillers 350 therein to support the chip 323, and the chip 323 is deviated from the chip 312 horizontally in a direction toward the first bonding wires 341 connected to the first chip module 31; the plurality of second bonding wires 342 for electrically connecting the bond pads 323a and 324a of the second chip module 32 to the chip carrier 30; and the encapsulant 36 deposed on the chip carrier 30 for encapsulating the first and the second chip modules 31 and 32 and the first and the second bonding wires 341 and 342.
Referring to further
As shown in
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Through the foregoing fabrication method, a multichip stacking structure disclosed in the present invention comprises: the chip carrier 30, the first chip module 31 having the plurality of first chips 311 and 312, wherein the first chips 311 and 312 respectively have bond pads 311a and 312a deposed at edges of surfaces thereof and the first chips 311 and 312 are stacked on the chip carrier 30 in the step-like manner to expose the bond pads 311a and 312a; the plurality of first bonding wires 341 for electrically connecting the bond pads 311a and 312a to the chip carrier 30; the second chip module 32 having the plurality of second chips 323 and 324, wherein the second chips 323 and 324 respectively have bond pads 323a and 324a deposed at edges of surface thereof, and the second chips 323 and 324 are stacked on the first chip module 31 to expose the bond pads 323a and 324a, the bottom chip (i.e. the chip 323) of the second chip module 32 is stacked on a top chip (i.e. the chip 312) of the first chip module 31 by the adhesive film 352 mounted therebetween, where the portion of the first bonding wire 341 connected to the chip 312 between the chips 312 and 323 are covered by the adhesive film 352, and the chip 323 is deviated from the chip 312 horizontally in a direction toward the first bonding wires 341 connected to the first chip module 31; the plurality of second bonding wires 342 for electrically connecting the second bond pads 323a and 324a of the second chip module 32 to the chip carrier 30, and the encapsulant 36 deposed on the chip carrier 30 for encapsulating the first and the second chip modules 31 and 32 and the first and the second bonding wires 341 and 342.
Referring to further
As shown in the
In addition, a chip 311 of the first chip module 31 can be electrically connected to the chip carrier 30 by the first bonding wires 341 using a conventional wire bonding method or a reverse wire bond method.
Referring to further
In addition, both a first and a second chip modules 31 and 32 are not limited to have only two chips. If n chips are to be stacked, the sum of the total projected length of the chips should still remain (S+L). As compared to the sum of the total projection length of S+(n−1)L in the conventional technology in which the plurality of chips are stacked toward a single direction, the total projection length of the chips in the stacking structure of the present invention is (S+(n−1)L)−(S+L)=(n−2)L less.
Moreover, a third chip module can be also stacked on the second chip module. Similarly, it is achieved by deposing the bottom chip of the third chip module on the top chip of the second chip module in a horizontal direction towards the second bonding wires by an adhesive layer or film.
Referring to further
The present embodiment is similar to the foregoing embodiments except that a first chip module 31 is mounted on a chip carrier 30 and a plurality of first bonding wires 341 is used for electrically connecting the first chip module 31 to the chip carrier 30 before that a second chip module having at least one chip 323 is mounted on the first chip module 31 by an adhesive layer 351 having fillers 350 therein to support the chip 323 (as shown in
Thus, according to the multichip stacking structure of the invention, the multiple chips each having the bond pad disposed on one side are sequentially stacked on the chip carrier in a step-like manner to form a first chip module. Then a plurality of first bonding wires are used to electrically connect the first chip module to the chip carrier. The numbers of chips to be stacked can be up to the maximum that can be packaged on the carrier. Then, the bottom chip of the second chip module is deposed on the top chip of the first chip module by the adhesive layer having filters therein for support the bottom chip or the adhesive film for covering the portion of the first bonding wire between the bottom chip of the second chip module and the top chip of the first chip module in a way that the bottom chip is deviated from the top chip horizontally in a direction toward the first bonding wires of the first chip module. Then remaining chips for the second chip module are stacked on the bottom chip in a manner as the stacking process for stacking chips of the first chip module. In such way, the problem that all chips deposed towards one direction is prevented and as a result more chips can be stacked. Moreover, the additional costs and fabrication steps for the additional deposing of buffering element in the prior art can be also eliminated. The multiple stacking structure provided by the present invention thus provides a solution to perform multiple chip stacking free from increasing package area and height, and is suitable for a light-weighted, small and low profile electronic device.
Moreover, the additional costs and fabrication steps for the additional deposing of buffering element in the prior art can be also eliminated. The multiple stacking structure provided by the present invention thus provides a solution to proceed multiple chip stacking without the need to increase package area and height, and is suitable for a lightweight, small and low profile electronic device.
The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 096102616 | Jan 2007 | TW | national |
| 096148169 | Dec 2007 | TW | national |
