Increased I/O semiconductor package and method of making same

Information

  • Patent Grant
  • 8125064
  • Patent Number
    8,125,064
  • Date Filed
    Monday, July 28, 2008
    16 years ago
  • Date Issued
    Tuesday, February 28, 2012
    12 years ago
Abstract
In accordance with the present invention, there is provided a semiconductor package and a fabrication method thereof. The semiconductor package is provided with a substrate made of metal, thereby improving efficiency of thermal emission from a semiconductor die mounted to the substrate, and simplifying the fabrication process for the substrate which reduces fabricating costs. Further, unlike a conventional land, a rivet electrically insulated with the substrate is inserted into a corresponding hole of the substrate, the upper and lower surfaces of the rivet being removed to form land, thereby simplifying the fabrication process for the substrate which further reduces fabricating costs.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

Not Applicable


STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT

Not Applicable


BACKGROUND OF THE INVENTION

1. Field of the Invention


The invention relates generally to a semiconductor package and a fabricating method thereof.


2. Description of the Related Art


Generally, a substrate for a printed circuit board (PCB) and a lead frame have been used as an electrical media in a semiconductor package. The substrate for the PCB is fabricated by forming an insulation layer, forming at least one via in the insulation layer, and thereafter filling the via with metal to form a conductive via. Then, fabrication of the substrate is continued by forming a conductive pattern and at least one land on upper and lower surfaces of the insulation layer, respectively.


The substrate for PCB is mainly an insulator such as thermal-setting resin, which has a low thermal conductivity not great enough to dissipate heat generated from a semiconductor die mounted thereon. Further, the process for forming a conductive via, a conductive pattern and a land on the substrate for PCB is accomplished through various steps, so that the productivity is decreased due to complexity of fabrication processes. Thus, fabricating costs for the substrate are increased due to complexity of the process.


Meanwhile, in order to solve the problem, a lead frame package is provided with a frame having a lead serving as input/output terminals. Consequently, the above-described problem of the fabrication of the substrate for PCB is solved by the lead frame package, but the number of input/output leads is limited by forming the input/output leads only in a peripheral area of the semiconductor die.


BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided a semiconductor package and a fabrication method thereof. The semiconductor package is provided with a substrate made of metal, thereby improving efficiency of thermal emission from a semiconductor die mounted to the substrate, and simplifying the fabrication process for the substrate which reduces fabricating costs. Further, unlike a conventional land, a rivet electrically insulated with the substrate is inserted into a corresponding hole of the substrate, the upper and lower surfaces of the rivet being removed to form land, thereby simplifying the fabrication process for the substrate which further reduces fabricating costs. The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.





BRIEF DESCRIPTION OF THE DRAWINGS

These, as well as other features of the present invention, will become more apparent upon reference to the drawings wherein:



FIG. 1A is a bottom plan view of a semiconductor package according to an exemplary embodiment of the present invention;



FIG. 1B is a cross-sectional view taken along 1B-1B of FIG. 1A;



FIG. 2A is a bottom plan view of a semiconductor package according to another exemplary embodiment of the present invention;



FIG. 2B is a cross-sectional view taken along 2B-2B of FIG. 2A;



FIG. 3A is a bottom plan view of a semiconductor package according to another exemplary embodiment of the present invention;



FIG. 3B is a cross-sectional view taken along 3B-3B of FIG. 3A;



FIG. 3C is a cross-sectional view taken along 3C-3C of FIG. 3A;



FIG. 4A is a bottom plan view of a semiconductor package according to another exemplary embodiment of the present invention;



FIG. 4B is a cross-sectional view taken along 4B-4B of FIG. 4A;



FIG. 5 is a cross-sectional view of a semiconductor package according to still another exemplary embodiment of the present invention;



FIG. 6 is a cross-sectional view of a semiconductor package according to still another exemplary embodiment of the present invention;



FIG. 7 is a cross-sectional view of a semiconductor package according to still another exemplary embodiment of the present invention;



FIG. 8 is a cross-sectional view of a semiconductor package according to still another exemplary embodiment of the present invention;



FIG. 9 is a flow chart explaining an exemplary fabrication method for the semiconductor package shown in FIGS. 1A and 1B;



FIGS. 10A through 10H are cross-sectional views illustrating an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package shown in FIGS. 1A and 1B;



FIG. 11 is a flow chart explaining an exemplary fabrication method for the semiconductor package shown in FIG. 7; and



FIGS. 12A through 12I are cross-sectional views illustrating an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package shown in FIG. 7.





Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements.


DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings wherein the showings are for purposes of illustrating various embodiments of the present invention only, and not for purposes of limiting the same, FIG. 1A illustrates a substrate 110 and a land 120 used for a semiconductor package 100 according to an exemplary embodiment of the present invention.


Referring to FIGS. 1A and 1B, the semiconductor package 100 may include a substrate 110, a land 120 penetrating the substrate 110, an adhesive 130 formed on an upper portion of the substrate 110, a semiconductor die 140 mounted on an upper portion of the adhesive 130, a conductive wire 150 electrically coupling the land 120 and the semiconductor die 140, an encapsulant 160 encapsulating the semiconductor die 140 and the conductive wire 150, and a solder ball 170 formed on a lower portion of the land 120.


The substrate 110 is preferably formed in a plate shape and is provided with an area for mounting the semiconductor die 140. In addition, the substrate 110 includes a patterned metal layer 111 defining a plurality of holes 111a within the substrate 110, and an insulation layer 112 formed along an outer portion of the patterned metal layer 111.


The patterned metal layer 111 formed in a plate shape is provided with a plurality of holes 111a as indicated above. The layer 111 can be made of a metal alloy including one or more metals selected from metals such as copper, aluminum, nickel and the like. Accordingly, the layer 111 increases thermal conductivity of the substrate 110, and thus heat generated from the semiconductor die 140 disposed on an upper portion of the patterned metal layer 111 as a heatproof plate is easily dissipated outside the semiconductor device 100.


Further, since the substrate 110 using the patterned metal layer 111 is made of metal, warpage due to heat generated from the substrate 110 can be prevented. The thickness of the substrate 110 may be from about 0.2 mm to 1.0 mm for preventing warpage, but not limited thereto.


The insulation layer 112 is formed along an outer surface of the patterned metal layer 111. In other words, the insulation layer 112 is formed along an inner wall of the holes 111a formed within the patterned metal layer 111, in addition to upper and lower surfaces of the layer 111. The insulation layer 112 may be made of insulation resin. The insulation layer 112 may be formed by coating, spraying, vacuum printing, or dipping the patterned metal layer 111 into a resin bath, though the present mention is not limited to any particular method for forming the insulation layer 112. Accordingly, the insulation layer 112 allows the patterned metal layer 111 and the land 120 formed inside the holes 111a of the patterned metal layer 111 to be electrically independent.


Each land 120 is formed by filling one of the plurality of holes 110a collectively defined by the holes 111a as lined with the insulation layer 112 with a prescribed conductive material. Since the insulation layer 112 is already provided inside the holes 111a of the patterned metal layer 111, each land 120 is thus surrounded by the insulation layer 112. Further, each land 120 may be formed in to have a square, circular or triangular cross-sectional shape, though not being limited to these shapes. Each land 120 may be formed by selecting any one of gold, silver, copper, aluminum, solder, or combinations thereof. Further, each land 120 is exposed in the upper and lower surfaces of the substrate 110, and the conductive wire 150 and the solder ball 170 may be connected to respective ones of the exposed portions thereof.


The adhesive 130 is formed on an upper portion of the substrate 110. The adhesive 130 attaches the substrate 110 to the semiconductor die 140. Materials of the adhesive 130 may include an epoxy, an adhesive tape or their equivalent materials, though not being limited thereto. The semiconductor die 140 is attached to the upper portion of the substrate 110 with the adhesive 130. Although the only one semiconductor die 140 is shown, it is contemplated that a plurality of semiconductor dies 140 can be stacked within the semiconductor package 100. Further, the semiconductor die 140 is provided with a plurality of bond pads 141 on an upper portion thereof. Although the bond pads 141 are shown as protruding from the upper portion of the semiconductor die 140, the bond pads 141 may be formed inside the semiconductor die 140.


The conductive wires 150 electrically couple the bond pads 141 of the semiconductor die 140 to respective ones of the lands 120. Each conductive wire 150 is provided by normal wire bonding such that one end of the conductive wire 150 forms a ball bonding area on a bond pad 141 of the semiconductor die 150, and the other end of the conductive wire 150 forms a stitch bonding area on the exposed upper portion of a corresponding land 120. Additionally, although not shown in the drawings, the conductive wire 150 may be provided by standoff stitch bonding (SSB) that forms the ball bonding area on the land 120, and connects the ball bonding area with a stud bump formed on the corresponding bond pad 141 of the semiconductor die 140.


The encapsulant 160 performs encapsulation covering the semiconductor die 140 and the conductive wire 150. The encapsulant 160 protects the semiconductor die 140 and the conductive wire 150 from external shock. The encapsulant 150 may be selected from one of epoxy resin, silicone resin or equivalent materials, but is not limited thereto.


Each solder ball 170 is formed on the exposed lower portion of a corresponding land 120. Further, each solder ball 170 may be electrically coupled with an external circuit. Each solder ball 170 can be made of a metal alloy including one or more metals selected from metals such as tin (Sn), lead (Pb) or silver (Ag) and the like, but is not limited thereto.


As indicated above, in the semiconductor package 100, the substrate 110 including the patterned metal layer 111 made of metal plays a role of a heatproof plate, thereby dissipating heat generated from the semiconductor die 140 to the outside. Additionally, the semiconductor package 100 has reduced susceptibility to warpage attributable to heat generated from the substrate 110. The semiconductor package 100 may have a number of the solder balls 180 commensurate to that of a conventional BGA (Ball Grid Array) package. The substrate 110 can be formed by a relatively simple process for etching a metal layer and an insulation layer so as to save fabricating costs in relation thereto.


Hereinafter, the structure of the semiconductor package 200 according to another exemplary embodiment of the present invention will be explained. Common reference numerals are used throughout the drawings and the detailed description to indicate the same element, and the differences between the above exemplary embodiments will be explained in detail below.


Referring to FIGS. 2A and 2B, the semiconductor 200 may include a substrate 210, at least one land 220 formed on the substrate 210, a first semiconductor die 240 mounted to the substrate 210, a conductive bump 242 electrically coupling the first semiconductor die 240 to the land 220, an underfill 243 formed between the substrate 210 and the first semiconductor die 240, a second semiconductor die 245 stacked upon an upper portion of the first semiconductor die 240, at least one conductive wire 250 electrically coupling the second semiconductor die 245 and the land 220, an encapsulant 160 formed on an upper portion of the substrate 210, and at least one solder ball 270 formed on a lower portion of the substrate 210 and electrically coupled to the land 220.


The substrate 210 may include a patterned metal layer 211 defining a plurality of holes 211a, and having an insulation layer 212 formed along an outer portion of the patterned metal layer 211. The insulation layer 212 is formed inside the holes 211a, in addition to upper and lower surfaces of the patterned metal layer 211. However, the insulation layer 212 is formed along an inner wall of each of the holes 211a instead of completely filling the holes 211a of the patterned metal layer 211. As a result, the holes 210a collectively defined by the holes 211a as lined with the insulation layer 212 are of sufficient size or diameter to form respective ones of the lands 220.


Each land 220 is formed completely by filling the inside each hole 210a of the substrate 210 with a conductive metal material. The lands 220 are also formed in areas of the substrate 210 so as to be operative to electrically connect the first semiconductor die 240 directly to the solder balls 270 through the use of the lands 220. The structural and functional attributes of the lands 220 is the same as the lands 120 in the above-described exemplary embodiment.


The first semiconductor die 240 is mounted in a flip-chip arrangement on the upper portion of the substrate 210. The first semiconductor die 240 is provided with bond pads 241 on one surface thereof, the bond pads 241 being arranged to be electrically coupled to respective ones of the lands 220. In this regard, the conductive bumps 242 electrically couple the bond pads 241 of the first semiconductor die 240 to respective ones of the lands 220. The conductive bumps 242 connect the bond pads 241 of the first semiconductor die 240 to the lands 220, thereby reducing the length in comparison with connection by wire and then reducing noise of inputted/outputted electric signals.


The underfill 243 is formed between the first semiconductor die 240 and the substrate 210. The underfill 243 is formed using epoxy, generally. The underfill 243 reduces stress applied to the first semiconductor die 240 due to difference of the coefficient of thermal expansion between the first semiconductor die 240 and the substrate 210.


The second semiconductor die 245 is adhered to the upper portion of the first semiconductor die 240 using an adhesive 244. The second semiconductor die 245 is the same as the semiconductor die 140 of the semiconductor package 100 as explained above, except that the adhesive 244 is formed on the upper portion of the first semiconductor die 241.


The conductive wires 250 shown in FIG. 2B electrically couple the bond pads 246 of the second semiconductor die 245 to the lands 220. The conductive wires 250 are the same as the conductive wires 150 of the semiconductor package 100 as explained above, except that the conductive wires 250 are electrically connected to the second semiconductor die 245 in the semiconductor package 200.


The solder balls 270 are formed on a lower surface of the substrate 210 and electrically coupled with respective ones of the lands 220. The solder balls 270 are also formed so as to input and output an electrical signal from the semiconductor package 200. The solder balls 270 are the same as the solder balls 170 of the semiconductor package 100, as explained above.


As described above, the semiconductor package 200 is provided with the substrate 210 used as a heatproof plate. As a result, a thermal dissipation rate of the semiconductor die 240 is increased, with warpage due to heat generated from the substrate 210 being prevented and fabrication costs for the substrate 210 being reduced. Additionally, the substrate 210 may be fabricated with a relatively simple process, and provide the same number of the solder balls 270 as a conventional BGA package. The substrate 210 corresponding to a filp-chip shaped semiconductor die can reduce noise of input/output signals.


Hereinafter, the structure of a semiconductor package 300 according to still another exemplary embodiment of the present invention will be explained in detail.


Referring to FIGS. 3A and 3B, the semiconductor package 300 according to still another exemplary embodiment of the present invention may include a substrate 310, at least one land 120, an adhesive 130, a semiconductor die 140, a conductive wire 150, an encapsulant 160 and at least one solder ball 170 electrically connected to the land 120.


The substrate 310 may include a patterned metal layer 311 defining a plurality of holes 311a, and an insulation layer 312 formed on the patterned metal layer 311. Further, the substrate 310 of the semiconductor package 300 is provided with at least one hole 310a collectively defined by the hole 311a and the insulation layer 312 for accommodating a land 120 in the same manner described above in relation to the semiconductor package 100. The substrate 310 may further define one or more penetration areas or openings 313 in prescribed portions thereof. Each penetration opening 313 extends through the substrate 310, and is defined by an opening in patterned metal layer 311 which is covered or lined with the insulation layer 312, similar to the manner in which each of the holes 310a are formed. The penetration openings 313 each preferably have a generally elliptical as shown, though other configurations such as a circular, triangular, square or star shape are contemplated to be within the spirit and scope of the present invention. Each penetration opening 313 is ultimately filled with the encapsulant 160. Accordingly, the penetration openings 313 increase a surface area in which the encapsulant 160 is engaged with the substrate 310, thereby increasing the adhesion force between the substrate 310 and the encapsulant 160.


As described above, the semiconductor 300 of the present invention is provided with the substrate 310 serving as a heatproof plate, so as to easily dissipate heat generated from the semiconductor die 140, the substrate configuration also saving fabrication costs, preventing warpage due to heat generated from the semiconductor die 140, and defining the same number of solder balls 170 as a conventional BGA package. In addition, the filling of the encapsulant 160 into the penetration opening(s) 313 increases the adhesion force between the substrate 310 and the encapsulant 160.


Hereinafter, a semiconductor package 400 according to still another exemplary embodiment of the present invention will be explained in detail.


Referring to FIGS. 4A and 4B, the semiconductor package 400 according to still another exemplary embodiment of the present invention may include the substrate 410, a plurality of lands 420 penetrating and thus extending through the substrate 410, an adhesive 130, a semiconductor die 140, a conductive wire 450 electrically coupling the lands 420 to the semiconductor die 140, an encapsulant 160 and solder balls 170 electrically coupled to respective ones of the lands 420.


The substrate 410 is formed in a plate shape and may include a patterned metal layer 411 defining a plurality of holes 411a, an insulation layer 412 formed on at least a portion of the patterned metal layer 411 and at least one penetration area or opening 313 penetrating or extending through the substrate 410. The holes 410a of the substrate 410 which are each collectively defined by a hole 411a as internally coated by the insulation layer 412 may be arranged in a radial pattern about a center of the substrate 410 as shown in FIG. 4A. Further, although not shown in the drawings, the holes 410a may be arranged in a crossing pattern on the substrate 410.


Each land 420 is formed by filling a respective one of the holes 410a of the substrate 410 with a conductive metal material as described above in relation to other embodiments. Accordingly, the lands 420 are also arranged in a generally radial pattern or a crossing pattern about a center of the substrate 410. The lands 420 are electrically coupled with respective ones of the conductive wires 450, which are in turn electrically coupled to respective ones of the bond pads 141 of the semiconductor die 140. The spacing and arrangement of the lands 420 is such that the sweeping of the conductive wires 450 may be prevented during the encapsulation process to form the encapsulant 160, so as to prevent an electrical short or cross from being mutually generated.


As indicated above, the conductive wires 450 electrically couple the lands 420 to the bond pads 141 of the semiconductor die 140. Further, the lands 420 are arranged in a radial pattern or a crossing pattern so that the conductive wires 450 have a maximum spacing or separation distance from each other. Accordingly, the conductive wires 450 are less susceptible to sweeping in the encapsulation process, thereby preventing an electrical short or cross from being mutually generated. As also indicated above, the semiconductor package 400 is provided with the substrate 410 which functions as a heatproof plate so as to dissipate heat generated from the semiconductor die 140 easily, and is less susceptible to warpage due to heat generated from the semiconductor die 140.


Hereinafter, the structure of a semiconductor package 500 according to still another exemplary embodiment of the present invention will be explained in detail.


Referring to FIG. 5, the semiconductor package 500 may include a substrate 510, at least one land 520 penetrating or extending through the substrate 510, an adhesive 530 formed on the substrate 510, at least one semiconductor die 540 attached to the substrate 510 with the adhesive 530, at least one conductive wire 550 electrically coupling the semiconductor die 540 to the land 520, an encapsulant 160 and a solder ball 170 electrically connected to the land 520.


The substrate 510 includes a patterned metal layer 511 defining holes 511a and an insulation layer 512 covering at least a portion of the patterned metal layer 511. The substrate also includes holes 510a which are each collectively defined by one of the holes 511a as internally coated with the insulation layer 512, each of the holes 510a accommodating a respective one of the lands 520.


Further, the substrate 510 defines at least one step 510b, which effectively creates a an inner portion of a first thickness, a middle portion which circumvents the inner portion and is of a second thickness exceeding the first thickness, and a peripheral outer portion which circumvents the middle portion and is of a third thickness exceeding the second thickness. The semiconductor die 540 is mounted to the center of the inner portion of the substrate 510.


A plurality of lands 520 is disposed in the substrate 510 within respective ones of the holes 510a thereof. As seen in FIG. 5, the holes 510a are of differing heights, depending on which of the inner, middle and outer portions of the substrate in which they are positioned. As a result, certain sets or groups of the lands 520 are also of differing heights or thicknesses, depending on which of the inner, middle and outer portions in which they are located. In other words, each land 520 is formed at the same height or thickness of that portion of the substrate 510 in which it is located. The lands 520 are electrically connected to the semiconductor die 540 by the conductive wires 550. Accordingly, the lands 520 are elevated higher toward the outer portion of the substrate 510, thus mitigating against the sweeping of the conductive wires 550 in the encapsulation process to prevent the conductive wires 550 from crossing or shorting.


At least one semiconductor die 540 may be mounted to the central area of the inner portion of the substrate 510. The semiconductor die 540 is provided with bond pads 541 in an upper portion of the semiconductor die 540, and the semiconductor die 540 may be stacked using a portion that the bond pads 541 are not formed upon. Although three semiconductor dies 540 are stacked are shown in FIG. 5, the present invention is not limited to any particular number or arrangement of semiconductor dies 540.


The conductive wires 550 electrically couple the bond pads 541 of the semiconductor dies 540 to respective ones of the lands 520. Further, the height of the lands 520 is formed to be higher toward the outer portion of the substrate 510 as indicated above, and thus the conductive wires 550 extending to the bond pads 541 may be separated from each other by a corresponding distance. Accordingly, the sweeping of the conductive wires 550 may be mitigated or prevented in the encapsulation process used to form the package body 160, thereby preventing the conductive wires 550 from crossing or shorting. As also described above, the semiconductor package 500 is provided with the substrate 410 which serves as a heatproof plate so as to easily emit heat generated from the semiconductor die(s) 540, and is less susceptible to warpage due to heat generated from the semiconductor die(s) 540.


Hereinafter, the structure of a semiconductor package 600 according to still another exemplary embodiment of the present invention will be explained in detail.


Referring to FIG. 6, the semiconductor package 600 may include a substrate 610, at least one land 120, at least one lead 625 connected with a side portion of the substrate 610, an adhesive 130, at least one semiconductor die 140, at least one conductive wire 650, an encapsulant 660 and at least one solder ball 170 electrically connected to the land 120.


The substrate 610 is generally formed in a plate shape. The substrate 610 includes a patterned metal layer 611 which defines a plurality of holes 611a and is at least partially covered by an insulation layer 612. The substrate 610 also includes a plurality of holes 610a which are each collectively defined by a hole 611a as internally covered or coated with the insulation layer 612. Each hole 610a accommodates a respective one of the lands 620. Further, a peripheral portion of the substrate 610 is etched on a lower portion or surface of the substrate 610, thus forming a peripheral stepped portion 610b which is of a reduced thickness in comparison to the remainder of the substrate 610.


Each lead 625 is connected with the stepped portion 610b of the substrate 610 by a tape, an adhesive or the like, and is outwardly exposed through a side portion or surface of the encapsulant 660. The stepped portion 610b of the substrate 610 is covered with the insulation layer 612 and maintained in an insulated state, and thus the leads 625 can be electrically independent of the substrate 610. Further, the leads 625 can be electrically coupled to the semiconductor die 140 by the conductive wires 650.


The conductive wires 650 electrically couple the semiconductor die 140 to respective ones of the lands 120. Further, as described above, the conductive wires 650 may be used to electrically couple the semiconductor die 140 to the lead 625.


The encapsulant 660 covers the stepped portion 610b of the substrate 610, inner portions of the leads 625, the semiconductor die 140 and the conductive wires 650. Accordingly, the encapsulant 660 promotes bonding or adhesion between the stepped portion 610b of the substrate 610 and the leads 625. Further, as indicated above, the leads 625 protrude from a side surface of the encapsulant 660.


As described above, the semiconductor package 600 is provided with the lead(s) 625 so as to increase the number of terminals to be connected with an external circuit. Further, the semiconductor package 600 is provided with the substrate 610 made of metal, which is used as a heatproof plate, thus allowing the heat generated from the semiconductor die 140 to be dissipated easily, while being less susceptible to warpage attributable to the heat.


Hereinafter, the structure of a semiconductor package 700 according to still another exemplary embodiment of the present invention will be explained in detail.


Referring to FIG. 7, the semiconductor package 700 may include a substrate 710, at least one rivet 720 penetrating or extending through the substrate 710, an adhesive 130, at least one semiconductor die 140, at least one conductive wire 150, an encapsulant 160 and at least one solder ball 170 electrically connected to the rivet 720.


The substrate 710 is formed in a plate shape and is provided with a plurality of holes 710a. Further, the substrate 710 may include a patterned metal layer 711 which defines a plurality of holes 711a and is at least partially covered by an insulation layer 712. Each of the holes 710a is collectively defined by a hole 711a and a small portion of the insulation layer 712.


Each rivet 720 is inserted into a respective one of the holes 710a of the substrate 710. An upper portion of each rivet 720 has a larger diameter rather than that of the hole 710a of the substrate 710, and thus the rivet 720 is fixed to the substrate 710 to prevent the rivet 720 from slipping through to a lower portion of the substrate 710. Each rivet 720 may include an outer insulation film 721 which directly contacts the substrate 710 and is open in both directions perpendicular to the substrate 710, and an internal land metal layer 722 which is formed by filling the interior of the insulation film 721 with a conductive metal material. The insulation film 721 insulates the substrate 710 from the land metal layer 722 of the rivet 720.


The land metal layer 722 has one end which is exposed to an upper portion of the substrate 710 and an opposed end which is exposed to a lower portion of the substrate 710. The land metal layer 722 is provided with an upper portion having a diameter larger than that of the hole 710a of the substrate 710 so as to be fixed to the hole 710a of the substrate 710. The land metal layer 722 penetrates or extends through the substrate 710 so as to input and output electrical signals through the land metal layer 722.


As described above, the semiconductor package 700 is provided with the substrate 710 used as a heatproof plate, thereby easily dissipating heat generated from the semiconductor die 140 and being less susceptible to due to such heat. Further, the semiconductor package 700 is provided with the lands 720 within respective ones of the holes 710a of the substrate 710, thereby forming a conventional land, a conductive via and a conductive pattern structure in one process through a single structural element. Accordingly, the fabrication costs for the semiconductor package 700 can be saved through the resultant simplification of the process for forming lands on substrates.


Hereinafter, the structure of a semiconductor package 800 according to still another exemplary embodiment of the present invention will be explained in detail.


Referring to FIG. 8, the semiconductor package 800 may include a substrate 210, at least one land 220, a rerouting film 813 formed on an upper portion of the substrate 210, an adhesive 130 formed on an upper portion of the rerouting film 813, a semiconductor die 140, at least one conductive wire 150, an encapsulant 160 and at least one solder ball 270 electrically connected to the land 220.


The rerouting film 813 is formed on an upper portion of the substrate 210. The rerouting film 813 comprises an insulation film 814 extending in parallel to the substrate 210. The rerouting film 813 includes a first pattern 815 formed in an upper side of the insulation film 814, a second pattern 816 formed on a lower side of the insulation film 814 and conductive vias 817 connecting the first and second patterns 815 and 816 to each other in a prescribed pattern or arrangement. Each conductive via 817 is formed in a vertical direction to connect the first and second patterns 815 and 816. Each conductive via 817 may be hollow, and formed with metal along an inner wall of the rerouting film 813. Further, each conductive via 817 may be solid and formed by filling a complimentary opening in the rerouting film 813 with a conductive metal material. Further, the upper and lower portions of the rerouting film 813 may be formed with a separate polyamide layer 818 partially insulating the first and second patterns 815 and 816.


The first pattern 815 is electrically coupled to the lands 220 and hence the solder balls 270 by the vias 817 and the second pattern 816. The second pattern 816 may be interfaced to the lands 220 through the use of electrical coupling members 819. The configuration of the second pattern 816 and vias 817 allows for the electrical of the first pattern 815 to those lands 220 positioned in the substrate 810 beneath the semiconductor die 140. The first and second patterns 815, 816 are each electrically insulated from the semiconductor die 140. However, as indicated above, the second pattern 816 is electrically coupled with the first pattern 815 by the conductive vias 817.


As indicated above, the rerouting film 813 allows certain ones of the lands 220 to be formed beneath the semiconductor die 140. The conductive wires 850 electrically couple the bond pads 141 of the semiconductor die 140 to the first pattern 815 of the rerouting film 813. Accordingly, the conductive wires 850 electrically couple the semiconductor die 140 to the lands 220, and hence the solder balls 270, via the rerouting film 813. The rerouting film 813 effectively routes the signals from certain ones of the conductive wires 850 to those lands 220 which are located beneath the semiconductor die 140.


As described above, the semiconductor package 800 is provided with the substrate 210 which functions as a heatproof plate, so that the heat generated from the semiconductor die 140 is easily dissipated to the outside, with the substrate 210 also being less susceptible to warpage due to such heat. Further, the substrate 210 can be fabricated by a relatively simple process for etching a metal layer and forming an insulation layer, thus saving fabrication costs. Further, the semiconductor package 800 can be provided with a lot of input/output terminals regardless of a position of the semiconductor die 140 due to the inclusion of the rerouting film 813.


Hereinafter, a fabricating method of the semiconductor package 100 according to an exemplary embodiment of the present invention will be explained in detail.


Referring to FIG. 9, the fabrication method for the semiconductor package 100 according to an exemplary embodiment of the present invention includes steps of providing a metal layer (S1), forming a patterned metal layer (S2), forming an insulation layer (S3), forming a land (S4), attaching a semiconductor die (S5), bonding a wire (S6), performing encapsulation (S7) and attaching a solder ball (S8). The steps of FIG. 9 will be explained with reference to FIGS. 10A to 10H below.


Referring to FIGS. 9 and 10A, a metal layer 10 formed in a plate shape is provided (S1). The metal layer 10 is made of a metal material having high thermal conductivity to easily emit heat generated from a semiconductor die to the outside. The metal layer 10 can be made of copper, aluminum, nickel and their alloys.


Referring to FIGS. 9 and 10B, holes 111a are formed on the metal layer 10 and then a patterned metal layer 111 is formed (S2). A method for forming the holes 111a in the metal layer 10 may be accomplished by etching. Further, a mask for etching may be formed by attaching a tape or coating a photo-resist in an area except for the area to be formed with the holes 111a in the metal layer 10. In addition, a series of processes are performed to remove the tape or the photo-resist after etching. Further, the method for forming the holes 111a in the metal layer 10 may be accomplished by laser drilling.


Referring to FIGS. 9 and 10C, an insulation layer 112 is then formed on the patterned metal layer 111, the patterned metal layer 111a and the insulation layer 112 collectively forming a substrate 110 (S3). In order to form the insulation layer 112 on the patterned metal layer 111, an insulation material may be coated on upper and lower surfaces of the pattern metal layer 111. In this process, the insulation material is filled inside and thus coats the interior surfaces of the holes 111a. Further, a vacuum suction process may additionally be performed to form the holes 111a filled with the insulation material. As described above, the insulation layer 112 may be formed on the upper and lower surfaces of the patterned metal layer 111 and along an inner wall of the holes 111a. Holes 110a are defined by the coating of the internal walls of the holes 111a with the insulation layer 112.


Referring to FIGS. 9 and 10D, the lands 120 are formed in respective ones of the holes 110a (S4). The lands 120 is formed by filling the holes 110a of the substrate 110 with a suitable conductive metal material. Each land 120 may be formed by electroplating after spreading a conductivity plate on a bottom of the substrate 110 and using the conductivity plate as a seed. Of course, after forming each land 120, the conductivity plate is removed. Further, in case that each land is formed of 120 solder, the lands 120 may be formed by filling the holes 110a using solder screen printing.


Referring to FIGS. 9 and 10E, the semiconductor die 140 is attached to an upper portion of the substrate 110 (S5). The semiconductor die 140 is attached to the substrate 110 by an adhesive 130 applied to the lower surface thereof.


Referring to FIGS. 9 and 10F, the bond pads 141 of the semiconductor die 140 are then electrically coupled to respective ones of the lands 120 using the conductive wires 150 (S6). The conductive wires 150 may each be formed by normal wire bonding that forms a ball bonding area on a respective one of the bond pads 141 of the semiconductor die 140 using one end of the conductive wire 150, and forms a stitch bonding area on a respective one of the lands 120 using the other end of the conductive wire 150. Additionally, although not shown in the drawings, the ball bonding area may formed on the land 120, a stud bump may formed on the bond pad 141 of the semiconductor die 140, and the conductive wire 150 may be formed using a standoff stitch bonding which connects the ball bonding area with the stud bump.


Referring to FIGS. 9 and 10G, the encapsulant 160 is then formed on the upper portion of the substrate 110 (S7). The encapsulant 160 encapsulates the semiconductor die 140 and the conductive wires 150. The encapsulant 160 may be one selected from epoxy resin, silicone resin or equivalent materials.


Referring to FIGS. 9 and 10H, the solder balls 170 are then formed on the lower portion of the substrate 110 (S8). The solder balls 170 are electrically connected to respective ones of the lands 120. The solder balls 170 may each be made of a metal alloy including one or more metals selected from the group consisting of tin (Sn), lead (Pb), silver (Ag) or the like.


As described above, the semiconductor package 100 is provided with the substrate 110 which functions as a heatproof plate, so as to improve efficiency for emitting heat generated from the semiconductor die 140 to the outside, the substrate also being less susceptible to warpage due to such heat and defining the same number of the solder balls 170 as in a conventional BGA semiconductor package. Further, the semiconductor package 100 may be produced through a simplified manufacturing process, thus reducing fabrication costs.


Hereinafter, a fabricating method of the semiconductor package 700 according to still another exemplary embodiment of the present invention will be explained in detail.


Referring to FIG. 11, the fabrication method for the semiconductor package 700 may include the steps of providing a metal layer and an insulation layer (S1), forming a substrate (S2), forming a rivet (S3), inserting the rivet (S4), opening upper and lower portions of the rivet (S5), attaching a semiconductor die (S6), bonding wires (S7), performing encapsulation (S8) and attaching a solder ball (S9). The steps of FIG. 11 will be explained with reference to FIGS. 12A to 12I below.


Referring to FIGS. 11 and 12A, the metal layer 10 and the insulation layer 20 surrounding or covering an outer portion of the metal layer 10 are provided (S1).


Referring to FIGS. 11 and 12B, the substrate 710 having holes 710a is formed by etching the metal layer 10 and the insulation layer 20 (S2). The substrate 710 includes a patterned metal layer 711 and an insulation layer 712 which collectively define the holes 710a.


Referring to FIGS. 11 and 12C, a rivet 30 including an insulation film 31 and a land metal layer 722 is provided (S3). The rivet 30 has a little smaller diameter than that of each hole 710a of the substrate 710, and an upper portion of the rivet 30 has a larger diameter than that of each hole 710a. Accordingly, the rivet 30 may be fixed in a prescribed position when inserted into a respective one of the holes 710a.


Referring to FIGS. 11 and 12D, the rivets 30 are inserted into respective ones of the holes 710a of the substrate 710 (S4). Each rivet 30 is inserted and fitted to a corresponding hole 710a of the substrate 710, and an upper portion of the rivet 30 is supported by the substrate 710 and fixed thereto.


Referring to FIGS. 11 and 12E, the upper and lower surfaces of the rivet 30 are removed and an internal land metal layer 722 is exposed, thereby forming the land 720 (S5). In order to remove the upper and lower surfaces of the insulation film 31 originally surrounding the internal land metal layer 722, a process of grinding or etching may be performed. The upper and lower surfaces of the insulation film 31 are removed, the land metal layer 722 is exposed, thereby forming the land 720 which is capable of inputting and outputting electrical signals.


Referring to FIGS. 11 and 12F, the semiconductor die 140 is then attached to the upper portion of the substrate 710 (S6). The semiconductor die 140 is provided with a plurality of bond pads 141 in an upper portion of the semiconductor die 140 and attached to the substrate 710 through the adhesive 130 applied to a lower portion of the semiconductor die 140.


Referring to FIGS. 11 and 12G, the bond pads 141 of the semiconductor die 140 are electrically coupled to respective ones of the lands 720 using the conductive wires 150 (S7). Each conductive wire 150 may be formed by normal wire bonding that forms a ball bonding area on a respective one of the bond pads 141 of the semiconductor die 140, and forms a stitch bonding area on a respective one of the lands 720. Additionally, although not shown in the drawings, each conductive wire 150 may be formed by standoff stitch bonding that forms a ball bonding area on the land 720 and a stud bump on the bond pad 141, and connects them to each other.


Referring to FIGS. 11 and 12H, the semiconductor die 140 and the conductive wire 150 are encapsulated by the encapsulant 160 (S8). The encapsulant also covers a portion of the substrate 710. The encapsulant 160 protects internal elements of the semiconductor package 700 and may be selected from one of epoxy resin, silicone resin or equivalent materials.


Referring to FIGS. 11 and 12I, the solder balls 710 are then attached to the lower portion of the substrate 710 (S9). The solder balls 170 are electrically connected to respective ones of the lands 720, and provide a path electrically coupling the semiconductor die 140 and an external circuit. Each solder ball 170 can be made of a metal alloy of tin (Sn), lead (Pb), silver (Ag) and the like.


As described above, the semiconductor package 700 is provided with the substrate 710 made of metal, which functions as a heatproof plate, thereby allowing the heat generated from the semiconductor die 140 to be dissipated easily to the outside, the substrate 710 also being less susceptible to warpage due to such heat, and further reducing the fabricating costs of the semiconductor package 700. Further, the lands 720 are each formed by a simplified fabrication process involving the use of the rivets 30 as described above.


This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and fabricating process, may be implemented by one skilled in the art in view of this disclosure.

Claims
  • 1. A semiconductor package, comprising: a generally quadrangular substrate defining a central die mounting area and at least four peripheral edge segments, the substrate comprising a patterned metal layer and an insulation layer formed on at least a portion of the patterned metal layer, the substrate defining a plurality of holes which are segregated into at least four sets, the holes of each set being located between the central die mounting area and a respective one of the peripheral edge segments such that the holes of the sets are generally arranged in a pattern of concentric rings which at least partially circumvent the central die mounting area;a plurality of lands disposed within respective ones of the holes of the substrate;at least one semiconductor die mounted to the substrate:at least one electrical coupling member electrically connecting the semiconductor die to at least one of the lands; andan encapsulant covering at least the semiconductor die and the electrical coupling member.
  • 2. The semiconductor package of claim 1, wherein the patterned metal layer is made of a metal alloy including at least one metal selected from the group consisting of copper, aluminum, and nickel.
  • 3. The semiconductor package of claim 1, wherein the holes in the patterned metal layer are each internally coated by the insulation layer.
  • 4. The semiconductor package of claim 1, wherein the insulation layer is made of an insulation resin.
  • 5. The semiconductor package of claim 1, wherein each of the lands completely fills a corresponding one of the holes of the substrate.
  • 6. The semiconductor package of claim 1, wherein the substrate further includes at least one penetration opening formed therein.
  • 7. The semiconductor package of claim 6, the penetration opening is filled with the encapsulant.
  • 8. The semiconductor package of claim 1, wherein the lands are arranged in a generally radial pattern which extends from the central die mounting area of the substrate.
  • 9. The semiconductor package of claim 1, wherein the substrate is provided with at least one step so as to define an inner portion which is of a first thickness, a middle portion which circumvents the inner portion and is of a second thickness exceeding the first thickness, and a peripheral outer portion which circumvents the middle portion and is of a third thickness exceeding the second thickness.
  • 10. The semiconductor package of claim 9, wherein the lands are segregated into multiple sets which are of differing heights and disposed within respective ones of the inner, middle and outer portions of the substrate.
  • 11. The semiconductor package of claim 10, wherein the at least one semiconductor die comprises a plurality of stacked semiconductor dies mounted to the inner portion of the substrate and electrically connected to at least one of the lands of each of the sets thereof.
  • 12. The semiconductor package of claim 1, wherein the substrate defines a peripheral portion of reduced thickness.
  • 13. The semiconductor package of claim 12, wherein at least one lead is connected to the peripheral portion of the substrate, the lead protruding from the encapsulant.
  • 14. The semiconductor package of claim 13, wherein the encapsulant covers a portion of the lead and effectively fixes the lead to the substrate.
  • 15. The semiconductor package of claim 1, wherein a solder ball is electrically connected to each of the lands.
  • 16. The semiconductor package of claim 1, further comprising: a rerouting film disposed on the substrate and electrically connected to the lands by an internal electrical path;the semiconductor die being mounted to the rerouting film, with at least some of the lands being located beneath the semiconductor die, the electrical coupling member electrically connecting the semiconductor die to the rerouting film, and the encapsulant covering the semiconductor die, the electrical coupling member, and a portion of the rerouting film.
  • 17. A semiconductor package, comprising: a generally quadrangular substrate defining a central die mounting area and at least four peripheral edge segments, the substrate comprising a patterned metal layer and an insulation layer formed on at least a portion of the patterned metal layer, the patterned metal layer including a plurality of holes which are each internally coated by the insulation layer to collectively define a plurality of insulated holes in the substrate which are segregated into at least four sets, the insulated holes of each set being located between the central die mounting area and a respective one of the peripheral edge segments such that the insulated holes of the sets are generally arranged in a pattern of concentric rings which at least partially circumvent the central die mounting area;a plurality of lands disposed within respective ones of the insulated holes of the substrate;at least one semiconductor die mounted to the substrate;at least one electrical coupling member electrically connecting the semiconductor die to at least one of the lands; andan encapsulant covering the semiconductor die, the electrical coupling member, and a portion of the substrate.
  • 18. The semiconductor package of claim 17, wherein each of the lands defines opposed ends which are exposed in and substantially flush with the insulation layer.
  • 19. The semiconductor package of claim 17, wherein a solder ball is electrically connected to each of the lands.
  • 20. A semiconductor package, comprising: a generally quadrangular substrate defining a central die mounting area and at least four peripheral edge segments, the substrate comprising a patterned metal layer including a plurality of holes formed therein, and an insulation layer which encapsulates the patterned metal layer and internally coats each of the holes thereof such that the patterned metal layer and the insulation layer collectively define a plurality of insulated holes in the substrate which are segregated into at least four sets, the insulated holes of each set being located between the central die mounting area and a respective one of the peripheral edge segments such that the insulated holes of the sets are generally arranged in a pattern of concentric rings which at least partially circumvent the central die mounting area;a plurality of lands disposed within respective ones of the insulated holes of the substrate;at least one semiconductor die mounted to the substrate;at least one electrical coupling member electrically connecting the semiconductor die to at least one of the lands; andan encapsulant covering the semiconductor die, the electrical coupling member, and a portion of the substrate.
US Referenced Citations (333)
Number Name Date Kind
2596993 Gookin May 1952 A
3435815 Forcier Apr 1969 A
3734660 Davies et al. May 1973 A
3838984 Crane et al. Oct 1974 A
4054238 Lloyd et al. Oct 1977 A
4189342 Kock Feb 1980 A
4221925 Finley et al. Sep 1980 A
4258381 Inaba Mar 1981 A
4289922 Devlin Sep 1981 A
4301464 Otsuki et al. Nov 1981 A
4332537 Slepcevic Jun 1982 A
4417266 Grabbe Nov 1983 A
4451224 Harding May 1984 A
4530152 Roche et al. Jul 1985 A
4541003 Otsuka et al. Sep 1985 A
4646710 Schmid et al. Mar 1987 A
4707724 Suzuki et al. Nov 1987 A
4727633 Herrick Mar 1988 A
4737839 Burt Apr 1988 A
4756080 Thorp, Jr. et al. Jul 1988 A
4812896 Rothgery et al. Mar 1989 A
4862245 Pashby et al. Aug 1989 A
4862246 Masuda et al. Aug 1989 A
4907067 Derryberry Mar 1990 A
4920074 Shimizu et al. Apr 1990 A
4935803 Kalfus et al. Jun 1990 A
4942454 Mori et al. Jul 1990 A
4987475 Sclesinger et al. Jan 1991 A
5018003 Yasunaga May 1991 A
5029386 Chao et al. Jul 1991 A
5041902 McShane Aug 1991 A
5057900 Yamazaki Oct 1991 A
5059379 Tsutsumi et al. Oct 1991 A
5065223 Matsuki et al. Nov 1991 A
5070039 Johnson et al. Dec 1991 A
5087961 Long et al. Feb 1992 A
5091341 Asada et al. Feb 1992 A
5096852 Hobson et al. Mar 1992 A
5118298 Murphy Jun 1992 A
5122860 Kichuchi et al. Jun 1992 A
5134773 LeMaire et al. Aug 1992 A
5151039 Murphy Sep 1992 A
5157475 Yamaguchi Oct 1992 A
5157480 McShane et al. Oct 1992 A
5168368 Gow, 3rd et al. Dec 1992 A
5172213 Zimmerman Dec 1992 A
5172214 Casto Dec 1992 A
5175060 Enomoto et al. Dec 1992 A
5200362 Lin et al. Apr 1993 A
5200809 Kwon Apr 1993 A
5214845 King et al. Jun 1993 A
5216278 Lin et al. Jun 1993 A
5218231 Kudo Jun 1993 A
5221642 Burns Jun 1993 A
5250841 Sloan et al. Oct 1993 A
5252853 Michii Oct 1993 A
5258094 Furui et al. Nov 1993 A
5266834 Nishi et al. Nov 1993 A
5273938 Lin et al. Dec 1993 A
5277972 Sakumoto et al. Jan 1994 A
5278446 Nagaraj et al. Jan 1994 A
5279029 Burns Jan 1994 A
5281849 Singh Deo et al. Jan 1994 A
5285352 Pastore et al. Feb 1994 A
5294897 Notani et al. Mar 1994 A
5327008 Djennas et al. Jul 1994 A
5332864 Liang et al. Jul 1994 A
5335771 Murphy Aug 1994 A
5336931 Juskey et al. Aug 1994 A
5343076 Katayama et al. Aug 1994 A
5358905 Chiu Oct 1994 A
5365106 Watanabe Nov 1994 A
5381042 Lerner et al. Jan 1995 A
5391439 Tomita et al. Feb 1995 A
5397917 Ommen et al. Mar 1995 A
5406124 Morita et al. Apr 1995 A
5410180 Fujii et al. Apr 1995 A
5414299 Wang et al. May 1995 A
5417905 LeMaire et al. May 1995 A
5424576 Djennas et al. Jun 1995 A
5428248 Cha Jun 1995 A
5435057 Bindra et al. Jul 1995 A
5444301 Song et al. Aug 1995 A
5452511 Chang Sep 1995 A
5454905 Fogelson Oct 1995 A
5467032 Lee Nov 1995 A
5474958 Djennas et al. Dec 1995 A
5484274 Neu Jan 1996 A
5493151 Asada et al. Feb 1996 A
5508556 Lin Apr 1996 A
5517056 Bigler et al. May 1996 A
5521429 Aono et al. May 1996 A
5528076 Pavio Jun 1996 A
5534467 Rostoker Jul 1996 A
5539251 Iverson et al. Jul 1996 A
5543657 Diffenderfer et al. Aug 1996 A
5544412 Romero et al. Aug 1996 A
5545923 Barber Aug 1996 A
5581122 Chao et al. Dec 1996 A
5592019 Ueda et al. Jan 1997 A
5592025 Clark et al. Jan 1997 A
5594274 Suetaki Jan 1997 A
5595934 Kim Jan 1997 A
5604376 Hamburgen et al. Feb 1997 A
5608265 Kitano et al. Mar 1997 A
5608267 Mahulikar et al. Mar 1997 A
5625222 Yoneda et al. Apr 1997 A
5633528 Abbott et al. May 1997 A
5637922 Fillion et al. Jun 1997 A
5639990 Nishihara et al. Jun 1997 A
5640047 Nakashima Jun 1997 A
5641997 Ohta et al. Jun 1997 A
5643433 Fukase et al. Jul 1997 A
5644169 Chun Jul 1997 A
5646831 Manteghi Jul 1997 A
5650663 Parthasarathi Jul 1997 A
5661088 Tessier et al. Aug 1997 A
5665996 Williams et al. Sep 1997 A
5673479 Hawthorne Oct 1997 A
5683806 Sakumoto et al. Nov 1997 A
5683943 Yamada Nov 1997 A
5689135 Ball Nov 1997 A
5696666 Miles et al. Dec 1997 A
5701034 Marrs Dec 1997 A
5703407 Hori Dec 1997 A
5710064 Song et al. Jan 1998 A
5723899 Shin Mar 1998 A
5724233 Honda et al. Mar 1998 A
5726493 Yamashita Mar 1998 A
5736432 Mackessy Apr 1998 A
5745984 Cole, Jr. et al. May 1998 A
5753532 Sim May 1998 A
5753977 Kusaka et al. May 1998 A
5766972 Takahashi et al. Jun 1998 A
5770888 Song et al. Jun 1998 A
5776798 Quan et al. Jul 1998 A
5783861 Son Jul 1998 A
5801440 Chu et al. Sep 1998 A
5814877 Diffenderfer et al. Sep 1998 A
5814881 Alagaratnam et al. Sep 1998 A
5814883 Sawai et al. Sep 1998 A
5814884 Davis et al. Sep 1998 A
5817540 Wark Oct 1998 A
5818105 Kouda Oct 1998 A
5821457 Mosley et al. Oct 1998 A
5821615 Lee Oct 1998 A
5834830 Cho Nov 1998 A
5835988 Ishii Nov 1998 A
5844306 Fujita et al. Dec 1998 A
5854512 Manteghi Dec 1998 A
5856911 Riley Jan 1999 A
5859471 Kuraishi et al. Jan 1999 A
5866939 Shin et al. Feb 1999 A
5866942 Suzuki et al. Feb 1999 A
5871782 Choi Feb 1999 A
5874784 Aoki et al. Feb 1999 A
5877043 Alcoe et al. Mar 1999 A
5886397 Ewer Mar 1999 A
5973935 Schoenfeld et al. Oct 1999 A
5977630 Woodworth et al. Nov 1999 A
RE36773 Nomi et al. Jul 2000 E
6097089 Gaku et al. Aug 2000 A
6107679 Noguchi Aug 2000 A
6143981 Glenn Nov 2000 A
6166430 Yamaguchi Dec 2000 A
6169329 Farnworth et al. Jan 2001 B1
6177718 Kozono Jan 2001 B1
6181002 Juso et al. Jan 2001 B1
6184465 Corisis Feb 2001 B1
6184573 Pu Feb 2001 B1
6194777 Abbott et al. Feb 2001 B1
6197615 Song et al. Mar 2001 B1
6198171 Huang et al. Mar 2001 B1
6201186 Daniels et al. Mar 2001 B1
6201292 Yagi et al. Mar 2001 B1
6204554 Ewer et al. Mar 2001 B1
6208020 Minamio et al. Mar 2001 B1
6208021 Ohuchi et al. Mar 2001 B1
6208023 Nakayama et al. Mar 2001 B1
6211462 Carter, Jr. et al. Apr 2001 B1
6218731 Huang et al. Apr 2001 B1
6222258 Asano et al. Apr 2001 B1
6222259 Park et al. Apr 2001 B1
6225146 Yamaguchi et al. May 2001 B1
6229200 McClellan et al. May 2001 B1
6229205 Jeong et al. May 2001 B1
6239367 Hsuan et al. May 2001 B1
6239384 Smith et al. May 2001 B1
6242281 McClellan et al. Jun 2001 B1
6256200 Lam et al. Jul 2001 B1
6258629 Niones et al. Jul 2001 B1
6281566 Magni Aug 2001 B1
6282094 Lo et al. Aug 2001 B1
6282095 Houghton et al. Aug 2001 B1
6285075 Combs et al. Sep 2001 B1
6291271 Lee et al. Sep 2001 B1
6291273 Miyaki et al. Sep 2001 B1
6294100 Fan et al. Sep 2001 B1
6294830 Fjelstad Sep 2001 B1
6295977 Ripper et al. Oct 2001 B1
6297548 Moden et al. Oct 2001 B1
6303984 Corisis Oct 2001 B1
6303997 Lee Oct 2001 B1
6307272 Takahashi et al. Oct 2001 B1
6309909 Ohgiyama Oct 2001 B1
6316822 Venkateshwaran et al. Nov 2001 B1
6316838 Ozawa et al. Nov 2001 B1
6323550 Martin et al. Nov 2001 B1
6326243 Suzuya et al. Dec 2001 B1
6326244 Brooks et al. Dec 2001 B1
6326678 Karmezos et al. Dec 2001 B1
6335564 Pour Jan 2002 B1
6337510 Chun-Jen et al. Jan 2002 B1
6339255 Shin Jan 2002 B1
6348726 Bayan et al. Feb 2002 B1
6355502 Kang et al. Mar 2002 B1
6359221 Yamada et al. Mar 2002 B1
6362525 Rahim Mar 2002 B1
6369447 Mori Apr 2002 B2
6369454 Chung Apr 2002 B1
6373127 Baudouin et al. Apr 2002 B1
6376908 Gaku et al. Apr 2002 B1
6377464 Hashemi et al. Apr 2002 B1
6380048 Boon et al. Apr 2002 B1
6384472 Huang May 2002 B1
6388336 Venkateshwaran et al. May 2002 B1
6395578 Shin et al. May 2002 B1
6399415 Bayan et al. Jun 2002 B1
6400004 Fan et al. Jun 2002 B1
6400010 Murata Jun 2002 B1
6410979 Abe Jun 2002 B2
6414385 Huang et al. Jul 2002 B1
6420779 Sharma et al. Jul 2002 B1
6421013 Chung Jul 2002 B1
6429508 Gang Aug 2002 B1
6437429 Su et al. Aug 2002 B1
6444499 Swiss et al. Sep 2002 B1
6448633 Yee et al. Sep 2002 B1
6452279 Shimoda Sep 2002 B2
6459148 Chun-Jen et al. Oct 2002 B1
6464121 Reijinders Oct 2002 B2
6465883 Olofsson Oct 2002 B2
6472735 Isaak Oct 2002 B2
6475646 Park et al. Nov 2002 B2
6476469 Hung et al. Nov 2002 B2
6476474 Hung Nov 2002 B1
6482680 Khor et al. Nov 2002 B1
6483178 Chuang Nov 2002 B1
6492201 Haba Dec 2002 B1
6492718 Ohmori Dec 2002 B2
6498099 McClellan et al. Dec 2002 B1
6498392 Azuma Dec 2002 B2
6507096 Gang Jan 2003 B2
6507120 Lo et al. Jan 2003 B2
6518089 Coyle Feb 2003 B2
6525942 Huang et al. Feb 2003 B2
6534849 Gang Mar 2003 B1
6545332 Huang Apr 2003 B2
6545345 Glenn et al. Apr 2003 B1
6552421 Kishimoto et al. Apr 2003 B2
6559525 Huang May 2003 B2
6566168 Gang May 2003 B2
6580161 Kobayakawa Jun 2003 B2
6583503 Akram et al. Jun 2003 B2
6586274 Murata Jul 2003 B2
6603196 Lee et al. Aug 2003 B2
6624005 DiCaprio et al. Sep 2003 B1
6646339 Ku Nov 2003 B1
6667546 Huang et al. Dec 2003 B2
6677663 Ku et al. Jan 2004 B1
6686649 Matthews et al. Feb 2004 B1
6696752 Su et al. Feb 2004 B2
6700189 Shibata Mar 2004 B2
6713375 Shenoy Mar 2004 B2
6757178 Okabe et al. Jun 2004 B2
6800936 Kosemura et al. Oct 2004 B2
6812552 Islam et al. Nov 2004 B2
6828224 Iijima et al. Dec 2004 B2
6858919 Seo et al. Feb 2005 B2
6867492 Auburger et al. Mar 2005 B2
6878571 Isaak et al. Apr 2005 B2
6897552 Nakao May 2005 B2
6927478 Paek Aug 2005 B2
7002805 Lee et al. Feb 2006 B2
7005327 Kung et al. Feb 2006 B2
7015571 Chang et al. Mar 2006 B2
7053469 Koh et al. May 2006 B2
7102209 Bayan et al. Sep 2006 B1
7112285 Chakravorty Sep 2006 B2
7185426 Hiner et al. Mar 2007 B1
7211471 Foster May 2007 B1
7245007 Foster Jul 2007 B1
7253503 Fusaro et al. Aug 2007 B1
7528476 Ito May 2009 B2
7759581 Nakasato et al. Jul 2010 B2
20010008305 McClellan et al. Jul 2001 A1
20010014538 Kwan et al. Aug 2001 A1
20020011654 Kimura Jan 2002 A1
20020024122 Jung et al. Feb 2002 A1
20020027297 Ikenaga et al. Mar 2002 A1
20020038873 Hiyoshi Apr 2002 A1
20020072147 Sayanagi et al. Jun 2002 A1
20020111009 Huang et al. Aug 2002 A1
20020140061 Lee Oct 2002 A1
20020140068 Lee et al. Oct 2002 A1
20020140081 Chou et al. Oct 2002 A1
20020158318 Chen Oct 2002 A1
20020163015 Lee et al. Nov 2002 A1
20020167060 Buijsman et al. Nov 2002 A1
20030006055 Chien-Hung et al. Jan 2003 A1
20030030131 Lee et al. Feb 2003 A1
20030059644 Datta et al. Mar 2003 A1
20030064548 Isaak Apr 2003 A1
20030073265 Hu et al. Apr 2003 A1
20030102537 McLellan et al. Jun 2003 A1
20030164554 Fee et al. Sep 2003 A1
20030168719 Cheng et al. Sep 2003 A1
20030198032 Collander et al. Oct 2003 A1
20040027788 Chiu et al. Feb 2004 A1
20040056277 Karnezos Mar 2004 A1
20040061212 Karnezos Apr 2004 A1
20040061213 Karnezos Apr 2004 A1
20040063242 Karnezos Apr 2004 A1
20040063246 Karnezos Apr 2004 A1
20040065963 Karnezos Apr 2004 A1
20040080025 Kasahara et al. Apr 2004 A1
20040089926 Hsu et al. May 2004 A1
20040164387 Ikenaga et al. Aug 2004 A1
20040253803 Tomono et al. Dec 2004 A1
20060087020 Hirano et al. Apr 2006 A1
20060157843 Hwang Jul 2006 A1
20060231939 Kawabata et al. Oct 2006 A1
20070023202 Shibata et al. Feb 2007 A1
Foreign Referenced Citations (82)
Number Date Country
19734794 Aug 1997 DE
0393997 Oct 1990 EP
0459493 Dec 1991 EP
0720225 Mar 1996 EP
0720234 Mar 1996 EP
0794572 Oct 1997 EP
0844665 May 1998 EP
0936671 Aug 1999 EP
0989608 Mar 2000 EP
1032037 Aug 2000 EP
55163868 Dec 1980 JP
5745959 Mar 1982 JP
58160096 Aug 1983 JP
59208756 Nov 1984 JP
59227143 Dec 1984 JP
60010756 Jan 1985 JP
60116239 Aug 1985 JP
60195957 Oct 1985 JP
60231349 Nov 1985 JP
6139555 Feb 1986 JP
61248541 Nov 1986 JP
629639 Jan 1987 JP
6333854 Feb 1988 JP
63067762 Mar 1988 JP
63188964 Aug 1988 JP
63205935 Aug 1988 JP
63233555 Sep 1988 JP
63249345 Oct 1988 JP
63289951 Nov 1988 JP
63316470 Dec 1988 JP
64054749 Mar 1989 JP
1106456 Apr 1989 JP
1175250 Jul 1989 JP
1205544 Aug 1989 JP
1251747 Oct 1989 JP
2129948 May 1990 JP
369248 Jul 1991 JP
3177060 Aug 1991 JP
4098864 Mar 1992 JP
5129473 May 1993 JP
5166992 Jul 1993 JP
5283460 Oct 1993 JP
6061401 Mar 1994 JP
692076 Apr 1994 JP
6140563 May 1994 JP
6260532 Sep 1994 JP
7297344 Nov 1995 JP
7312405 Nov 1995 JP
8064634 Mar 1996 JP
8083877 Mar 1996 JP
8125066 May 1996 JP
964284 Jun 1996 JP
8222682 Aug 1996 JP
8306853 Nov 1996 JP
98205 Jan 1997 JP
98206 Jan 1997 JP
98207 Jan 1997 JP
992775 Apr 1997 JP
9260568 Oct 1997 JP
9293822 Nov 1997 JP
10022447 Jan 1998 JP
10199934 Jul 1998 JP
10256240 Sep 1998 JP
11307675 Nov 1999 JP
2000150765 May 2000 JP
200160648 Mar 2001 JP
2002519848 Jul 2002 JP
200243497 Aug 2002 JP
941979 Jan 1994 KR
19940010938 May 1994 KR
19950018924 Jun 1995 KR
19950041844 Nov 1995 KR
19950044554 Nov 1995 KR
19950052621 Dec 1995 KR
1996074111 Dec 1996 KR
9772358 Nov 1997 KR
100220154 Jun 1999 KR
20000072714 Dec 2000 KR
20000086238 Dec 2000 KR
20020049944 Jun 2002 KR
9956316 Nov 1999 WO
9967821 Dec 1999 WO