INTEGRATED CIRCUIT CHIP AND PACKAGE

Abstract

An integrated circuit chip and a package supported by a device or a semiconductor chip are provided. The integrated circuit chip comprises a substrate, a device part, and a first integrated circuit chip. The device part is formed over the substrate, and the first integrated circuit chip is formed over the device part. The area occupied by the integrated circuit chip can be reduced. This reduction in area allows miniaturization of devices, cost reduction, improvement in productivity, and minimization of an occurrence of electrical interference between integrated circuit chips. As a result, it is possible to prevent degradation of the performance.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The implementation of this document will be described in detail with reference to the following drawings in which like numerals refer to like elements.

FIG. 1 a illustrates two conventional integrated circuit (IC) chips that are individually packaged;

FIG. 1 b illustrates another conventional packaging in which two IC chips are bonded together over one substrate through wires, wherein pads of the IC chips are electrically connected with respective pads of the substrate;

FIG. 1 c illustrates another conventional packaging in which two conventional IC chips are bonded together in a stack type through wires, wherein pads of the IC chips are electrically connected with respective pads of the substrate;

FIG. 2 illustrates an IC chip according to a first embodiment of the present invention;

FIG. 3 illustrates an IC chip according to a second embodiment of the present invention;

FIG. 4 illustrates an IC chip according to a third embodiment of the present invention;

FIG. 5 illustrates an IC chip according to a fourth embodiment of the present invention;

FIG. 6 illustrates an IC chip according to a fifth embodiment of the present invention; and

FIG. 7 illustrates an IC chip according to a sixth embodiment of the present invention.

Claims

1. An integrated circuit chip comprising: a substrate;a device part formed over the substrate; anda first integrated circuit chip formed over the device part.

2. The integrated circuit chip of claim 1, wherein the device part comprises at least two devices spaced apart from each other.

3. The integrated circuit chip of claim 2, wherein the device part is one of an active device and a passive device.

4. The integrated circuit chip of claim 1, further comprising one of a second integrated circuit chip and an additional device part, both formed over the substrate.

5. The integrated circuit chip of claim 4, wherein a height of the device part spaced apart from the substrate is greater than a height of the second integrated circuit chip or the additional device part.

6. The integrated circuit chip of claim 4, wherein the substrate is electrically coupled to the first integrated circuit chip through bonding wires.

7. The integrated circuit chip of claim 4, wherein the substrate is electrically coupled to the second integrated circuit chip through bonding wires.

8. The integrated circuit chip of claim 4, wherein the substrate is electrically coupled to the second integrated circuit chip through a mechanical contact based on a SMT (surface mount technology).

9. The integrated circuit chip of claim 4, wherein one of the first integrated circuit chip and the second integrated circuit chip is a chip receiving a RF (radio frequency) signal, and the other of the first integrated circuit chip and the second integrated circuit chip is a chip comprising a digital block where digital circuits are formed.

10. The integrated circuit chip of claim 1, further comprising a third integrated circuit chip formed over the first integrated circuit chip.

11. The integrated circuit chip of claim 10, wherein the third integrated circuit chip is electrically coupled to the substrate through bonding wires.

12. The integrated circuit chip of claim 10, wherein the third integrated circuit chip is electrically coupled to the first integrated circuit chip through bonding wires.

13. The integrated circuit chip of claim 10, wherein the third integrated circuit chip is a chip comprising a digital block wherein digital circuits are formed.

14. The integrated circuit chip of claim 1, further comprising a fourth integrated circuit chip formed over the substrate, wherein the first integrated circuit chip is formed over the device part and the fourth integrated circuit chip.

15. The integrated circuit chip of claim 14, wherein the substrate is electrically coupled to the fourth integrated circuit chip through a mechanical contact based on a SMT (surface mounting technology).

16. An integrated circuit package comprising the integrated circuit chip according to claim 1.