Embodiments of the present invention generally relate to the field of integrated circuit package design and, more particularly, to integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate.
With shrinking transistor size and more functionality incorporated into microelectronic devices, die to package substrate interconnect geometries will also need to be reduced. Currently, the die is connected to the package substrate using a solder joint connection commonly referred to as a flip-chip connection. Traditional flip chip processes become increasingly complex as bump pitch reduces because of the difficulty in under filling the space between the flip chip bumps.
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which:
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
Microelectronic die 102 is intended to represent any type of integrated circuit die. In one embodiment, microelectronic die 102 is a multi-core microprocessor. Microelectronic die 102 includes an active surface 104 which contains the electrical connections necessary to operate microelectronic die 102.
Microelectronic die 102 is held in place on at least one side by encapsulation material 106. Encapsulation material 106 includes at least one surface substantially planar to active surface 104. In one embodiment, active surface 104 is placed on a holding plate while encapsulation material 106 is disposed around microelectronic die 102. Encapsulation material 106 may extend over the back side (opposite active surface 104) of microelectronic die 102.
Microelectronic package core 108 may be included in first integrated circuit package element 100 to provide mechanical support and stability during the build-up process. Microelectronic package core 108 may have an opening in which microelectronic die 102 is disposed. In one embodiment microelectronic package core 108 is not included in first integrated circuit package element 100, and encapsulation material 106 may be used to a greater extent.
First dielectric material layer 110 is disposed on at least a portion of active surface 104 and encapsulation material 106. Build-up layers 112 are subsequently disposed on first dielectric material layer 110 using well known processing methods.
Conductive traces 114 are disposed on first dielectric material layer 110 and build-up layers 112 and are in electrical contact with active surface 104. Conductive contacts 116 couple with conductive traces 114 and allow first integrated circuit package element 100 to be electrically coupled, for example by a solder connection, to second integrated circuit package element 200, which is described below. In one embodiment, conductive contacts 116 include solder bumps. In another embodiment, conductive contacts 116 include lands.
Second integrated circuit package element 200 is coupled with first integrated circuit package element 100 to form an integrated circuit package. Second integrated circuit package element 200 may include a substrate core 202 to provide mechanical support. Well known processing methods may be utilized to form upper build-up layers 204 and lower build-up layers 206. In one embodiment, substrate core 202 is not included in second integrated circuit package element 200, and build-up layers alone, for example a multi-layer organic substrate, may be utilized.
Top conductive contacts 212 are disposed on top surface 208. Top conductive contacts 212 allow second integrated circuit package element 200 to be electrically coupled, for example by a solder connection, to first integrated circuit package element 100. In one embodiment, top conductive contacts 212 include solder bumps. In another embodiment, top conductive contacts 212 include lands.
Bottom conductive contacts 214 are disposed on bottom surface 208. Bottom conductive contacts 212 allow second integrated circuit package element 200 to be electrically coupled, for example by a socket connection, to other devices, for example a printed circuit board. In one embodiment, bottom conductive contacts 214 comprise a land grid array. In another embodiment, bottom conductive contacts 214 comprise a ball grid array. In another embodiment, bottom conductive contacts 214 comprise a pin grid array.
Conductive traces 216 are routed through second integrated circuit package element 200 to conductively couple top conductive contacts 212 with bottom conductive contacts 214.
Embedded components 218 may be included in the substrate of second integrated circuit package element 200. In one embodiment, embedded components 218 include at least one memory device. In another embodiment, embedded components 218 include at least one discrete component such as a capacitor, inductor, resistor, logic device or the like.
Second integrated circuit package element 200 is designed to transmit signals from a top pitch 220 to a bottom pitch 222. In one embodiment, top pitch 220 is as fine as practicable to be able to form solder joint connections between first integrated circuit package element 100 and second integrated circuit package element 200. In one embodiment, top pitch 220 is from about 80 to about 130 micrometers. In one embodiment, bottom pitch 222 is from about 400 to about 800 micrometers.
Processor(s) 402 may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, processors(s) 402 are Intel® compatible processors. Processor(s) 402 may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system.
Memory controller 404 may represent any type of chipset or control logic that interfaces system memory 406 with the other components of electronic appliance 400. In one embodiment, the connection between processor(s) 402 and memory controller 404 may be a point-to-point serial link. In another embodiment, memory controller 404 may be referred to as a north bridge.
System memory 406 may represent any type of memory device(s) used to store data and instructions that may have been or will be used by processor(s) 402. Typically, though the invention is not limited in this respect, system memory 406 will consist of dynamic random access memory (DRAM). In one embodiment, system memory 406 may consist of Rambus DRAM (RDRAM). In another embodiment, system memory 406 may consist of double data rate synchronous DRAM (DDRSDRAM).
Input/output (I/O) controller 408 may represent any type of chipset or control logic that interfaces I/O device(s) 412 with the other components of electronic appliance 400. In one embodiment, I/O controller 408 may be referred to as a south bridge. In another embodiment, I/O controller 408 may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003.
Network controller 410 may represent any type of device that allows electronic appliance 400 to communicate with other electronic appliances or devices. In one embodiment, network controller 410 may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller 410 may be an Ethernet network interface card.
Input/output (I/O) device(s) 412 may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance 400.
In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.
Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims.