BRIEF DESCRIPTION OF THE DRAWINGS
The above features, and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a cross-sectional view showing a semiconductor package having a semiconductor die and a PCB electrically connected to each other according to the prior art;
FIG. 2 is a top view of the conventional semiconductor package shown in FIG. 1.
FIG. 3 is a perspective view showing a semiconductor package according to a preferred embodiment of the present invention;
FIG. 4 is a sectional view taken along line B-B′ of the semiconductor package shown in FIG. 3;
FIG. 5 is a sectional view taken along line A-A′ of the semiconductor package shown in FIG. 3;
FIG. 6 is a top view of the semiconductor package shown in FIG. 3;
FIG. 7 is a perspective view of an interposer shown in FIG. 3;
FIG. 8 is a top view of the upper surface of a PCB shown in FIG. 3;
FIG. 9 is a partial sectional view of the PCB shown in FIG. 3; and
FIG. 10 is a partial sectional view of the interposer shown in FIG. 3.
DETAILED DESCRIPTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein is omitted to avoid making the subject matter of the present invention unclear.
FIG. 3 is a perspective view showing a semiconductor package according to a preferred embodiment of the present invention. FIG. 4 is a sectional view taken along line B-B′ of the semiconductor package shown in FIG. 3. FIG. 5 is a sectional view taken along line A-A′ of the semiconductor package shown in FIG. 3. FIG. 6 is a top view of the semiconductor package shown in FIG. 3. Referring to FIG. 3, the semiconductor package 200 according to the present embodiment includes a PCB 210 having a plurality of electric contacts 202 (not shown), an interposer 230, a semiconductor die 220, and a support member 201 inserted between the interposer 230 and the PCB 210. With reference to FIG. 4, the position of the electrical contacts 231b with regard to the PCB 210 and interposer 230. With reference to FIG. 5, the wiring 222a and 222b, above and below, respectively, interposer 230 is shown, With reference to FIG. 6, the interweaving of the wiring 222a and 222b with regard to the interposer in accordance with the principles of the invention.
FIG. 8 is a top view of the upper surface of PCB 210 shown in FIG. 3. The PCB 210 shown in FIG. 8 includes a plurality of first electrical contacts 202 and second electrical 231b. The interposer 230 and the semiconductor die 220 are seated on the PCB 210. The first electrical contacts 202 and second electrical contact 231b are formed on the upper surface of the PCB 210, on which the interposer 230 is seated.
Returning to FIG. 3, selected ones of the second electric terminals 221 on semiconductor die 220 are electrically connected to the electric terminals 231a via first wires 222a, and the remaining second electric terminals 221 are electrically connected to the second electric contacts 231b (FIG. 8) via second wires 222b. The first and second wires 222a and 222b are electrically connected by stitch bonding or wire bonding.
The first and second wires 222a and 222b may be wire-bonded by a capillary, which preferably is a high-precision ceramic-processed product and is used to attach gold wires for connecting a semiconductor die to a lead frame. The second wires 222b, which are connected to the second electric contacts 231b, may be formed so as to abut the bottom along the movement trajectory of the capillary. The thickness of the support member (particularly, solder resist) 201 may be similar to that of the bonded second wires 222b so that when the interposer 230 is seated the second wires 222b are not compressed.
Referring to FIG. 7, which is a perspective view of the interposer shown in FIG. 3, the interposer 230 includes a polyhedral body 234 having first and second surfaces facing each other, vias 232 extending through the first to the second surfaces, and first electric contacts 231a formed on the first surface.
The interposer 230 is seated on the PCB 210 so that the vias 232 are electrically connected to the corresponding first electric contacts 202.
FIG. 9 is a partial sectional view of the PCB shown in FIG. 3, and FIG. 10 is a partial sectional view of the interposer shown in FIG. 3. The second electric contacts 202 are electrically connected to the corresponding vias 232 via stud bumpers, which are preferably made of a gold material. Referring to FIGS. 9 and 10, each second electric contact 202 includes an electrode 202b made of gold and a solder bumper 202a formed on the electrode 202b. Each hole 232 is provided with an electrode 232a having a shape corresponding to that of the facing second electric contact 202 and a solder bumper (gold stud bump) 232b.
After aligning the solder bumpers 202a and (gold stud bump) 232b so that they abut each other, the second electric contacts 202 are completely bonded to the vias 232 through a heat treatment process (i.e. reflow).
The support member 201, which preferably is a type of solder resist, is positioned between the second electric contacts 202 so as to prevent the solder bumpers 202a and (gold stud bump) 232b from melting excessively during a heat treatment process (e.g. reflow) and electrically connecting to other adjacent second electric contacts. Preferably, the thickness of the support member 201 is larger than that of the solder bumpers 202a and 232b.
The semiconductor die 220 has a plurality of second electric terminals 221, some of which are electrically connected to the first electric terminals 231a, and the remaining second electric terminals 221 are connected to the bonding pad-type second electric contacts 231b.
As mentioned above, the semiconductor package including a semiconductor die according to the present invention is advantageous in that, by electrically connecting a PCB to the semiconductor die via an interposer electrically connected to the semiconductor die, wiring to an external input/output pin can be easily made, in terms of routing, through rewiring.
While the invention has been shown and described with reference to certain preferred embodiments thereof it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Patent Application
20080029871
