Patent Application
20060057763
(1) Field of the Invention
The invention relates to processes for the manufacture of integrated circuits and more particularly to the mounting of an integrated circuit chip onto a substrate by a surface mount method
(2) Background of the Invention and Description of Previous Art
Flip chip microelectronic assembly is the direct electrical connection of face-down electronic components or integrated circuit chips onto substrates, circuit boards, or carriers by means of conductive bumps on the chip bond pads. In contrast, wire bonding, the older technology which flip chip replaces, uses face-up chips with a wire connection to each pad. Flip chip components are predominantly semiconductor devices; however, components such as passive filters, detector arrays, and MEMs devices are also beginning to be used in flip chip form. Flip chip is also called Direct Chip Attach (DCA), a more descriptive term, since the chip is directly attached to the substrate, board, or carrier by the conductive bumps. IBM introduced flip chip interconnection in the early sixties for their mainframe computers, and has continued to use flip chip since then. Delco Electronics developed flip chips for automotive applications in the seventies. Delphi Delco currently places over 300,000 flip chip die per day into automotive electronics. Most electronic watches, and a growing percentage of cellular phones, pagers, and high speed microprocessors are assembled with flip chip.
One application of flip-chip technology is the manufacture of RFID (radio Frequency Identification) tags. These miniature rf transponders, also known as “smart labels” are embedded or otherwise attached on various articles to provide remote identification and location information, for example, for automobiles, credit cards, store merchandise, migratory birds, proximity detecting devices, and other objects which may need to be traced or identified. RFID tags are manufactured as flip-chip assemblies wherein the rf antenna is formed on a substrate, to which a tiny memory and processor integrated circuit chip is bonded. The memory/processor chip can connect with a host application through RF (Radio Frequency) communication. The RFID smart labels have a limited memory capacity (in the range of 32-256 bytes) that can be read or written to multiple times by means of a reader that connects to a computer. The labels do not need a separate power supply. They operate on transmitted rf radiation that is picked up by the antenna. The size of the labels is determined by size of the antenna and is approximately 3×3 cm (1.5×1.5 inch). A disadvantage of this is that the labels cannot be used on metal objects.
Currently, the RFID chips are bonded to the antenna bearing substrate with either a non-conducting adhesive (NCA) or an anisotropic-conductive adhesive (ACA). In either case, electrical connection is achieved through metal bumps on the IC chip which penetrate the adhesive and make direct contact to the rf antenna. Brady, et. al., U.S. Pat. No. 6,259,408 B1, attaches an RFID chip to an antenna which is printed on a substrate which may be a rigid material such as ceramic but can also be a flexible material such as a thin polyimide or polyester film. The antenna is formed of a polymer resin containing silver particles. Bonding of the metallic chip bumps to the antenna is accomplished by applying heat and downward pressure to the chip for a period of time.
An integrated circuit chip 12, shown in planar view in
The chip 12 is now flipped over and the bumps 18 aligned to the antenna terminal pads 10 through the adhesive 16. Referring to
Seidowski, et. al., German Patent Number DE-19905807 A1, teaches the roughening of the bump surface in the form of wedges, cones, or pyramids. These features penetrate any native film, such as a native oxide formed on an aluminum pattern, thus assuring a good ohmic contact when the bump is pressed onto the substrate.
The main disadvantage of the existing RFID tag assembly using the flip-chip process is still high manufacturing cost. This is driven mainly by low productivity, arising from the slow IC alignment and bonding process which involves the application of heat for an extended period under bonding pressure. A further problem with the use of ACA is that the interconnect pressure bonding and adhesive curing must be done on the placement machine which creates a serious production bottleneck. The high manufacturing cost and low productivity is still the main obstacle that prevents widespread adoption of the RFID tag. A variety of approaches have been proposed by other researchers to reduce the manufacturing cost. These approaches concentrate on reducing the cure time of the bonding adhesive and the use of cheaper substrate materials.
It is therefore desirable to have a method for forming a RFID smart tag assembly which will overcome the productivity problems created primarily by the need for bonding pressure when an ACA is used. The present invention improves the productivity of RFID tag assembly by a novel combination of physical IC structural (design) changes which permits the use of an ECA without the need for critical time consuming alignment of the chip with the substrate antenna terminal pads. Consequently the adhesive can be cured after removal of the assembly from the chip placement machine, thereby eliminating the processing bottleneck at this station.
The simplest footprint for mounting and interconnecting a standard SMD (surface mounted Device) embodies a chip 132 with a two terminal pad footprint which is illustrated in planar and cross-sectional view in
It is an object of this invention to provide a design of an interconnect structure for a RFID tag which permits the use of an ECA without requirement of critical alignment of the chip terminal pads or bumps to antenna terminals on the substrate.
It is another object of this invention to provide a design and assembly process of an interconnect structure for a RFID tag which significant improves productivity and lowers production cost.
It is yet another object of this invention to describe a design and assembly process of an interconnect structure for a RFID tag whereby terminal pads on the chip are connected directly to corresponding terminal pads on the substrate eliminates the need for forming bumps on the chip terminals.
It is yet another object of this invention to describe a design and assembly process of an interconnect structure for a RFID tag which eliminates the need for pressure application during adhesive curing.
It is yet another object of this invention to describe a design and assembly process of an interconnect structure for a RFID tag wherein the curing of the bonding adhesive is performed in a separate process step after removal of the assembly from the chip placement machine.
These objects are accomplished by designing the RFID chip terminal pads and the corresponding antenna terminal pads on the substrate in a way that the footprint of the connection complies with the footprint of standard discrete SMD. This provides a relatively large interconnect pad area which provides a wide alignment tolerance. The key benefit of designing and fabricating the RFID chip into the form of the standard discrete SMD footprint is that placement of the chip onto the substrate can be carried out with an SMT (Surface Mount Technology) placement machine which is well known in the assembly of printed circuit boards, and is capable of much greater productivity than conventional, critical alignment, flip chip bonding tools.
a through 1h are members of a flow diagram showing cross sections of the preparation and the mounting process of a RFID tag chip and its antenna bearing substrate according to a prior art procedure.
a and 2b are planar and cross sectional views respectively of a prior art standard discrete SMD chip.
a through 3f are members of a flow diagram showing cross sections of the preparation and the mounting process of a RFID tag chip and its antenna bearing substrate according to the procedure taught by the present invention.
a and 4b are a planar and cross sectional views respectively of a three terminal variation of the integrated circuit chip having a standard discrete SMD terminal footprint, as applied in the present invention.
In a first embodiment of this invention a novel assembly process for mounting an RFID tag on an antenna bearing substrate is described. A key feature of the process is the use of a chip of discrete SMD terminal footprint to mount and interconnect the chip to the substrate, using an isotropic electrically conductive adhesive.
Referring now to
In this embodiment the RFID integrated circuit chip has a width “W” between about 18 and 22 mils. and a length “L” between about 38 and 42 mils. which corresponds to a 0402 SMD footprint. The width “WT” of the antenna interconnect terminal pads 34 is between about 9.8 and 10.2 mils. and have a length of “W”.
The substrate 26 is next picked and sent to an in-line adhesive delivery tool which dispenses or prints an isotropic electrically conductive adhesive (ECA) 36 onto the antenna terminals 30 (
While the embodiments of this invention utilizes a two terminal standard discrete SMD footprint design to form a RFID tag chip assembly, it should be understood that variations in the footprint length to width ratio as well as extension to more than two terminals. Such a footprint is show in planar an cross section in
While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
