Patent Application
20140048326
1. Field of the Invention
The present invention relates to a multi-cavity wiring board for a semiconductor assembly with electromagnetic shielding, and more particularly to a multi-cavity wiring board that includes a plurality of cavities with lateral shielding sidewalls.
2. Description of Related Art
The semiconductor devices are susceptible to electromagnetic interference (EMI) or other inter-device interference, such as capacitive, inductive, conductive coupling when operated in a high frequency mode. These undesirable interferences may become increasingly serious when the semiconductor dies are placed closely together for the miniaturization purpose. Conventional approaches to isolate these devices include forming a conductive layer on the encapsulant or placing a metal cover over an assembly. For multi-chip assembly, however, the shielding must be formed over the individual semiconductor die prior to final encapsulation in order to reduce the interference between the semiconductor dies on a board.
U.S. Pat. No. 7,187,060 to Usui, U.S. Pat. No. 8,076,757 to Pagalla et al., and U.S. Pat. No. 8,093,691 to Fuentes et al., disclose various semiconductor devices in which a conductive layer is applied to a sealant or mold compound for EMI shielding after the semiconductor die is encapsulated. None of these approaches offers a proper EMI shielding or effective electromagnetic protection at the wiring board level especially when the semiconductor dies are disposed side-by-side on a board.
The present invention has been developed in view of such a situation, and an object thereof is to provide a wiring board having a plurality of cavities with lateral shielding sidewalls which can serve as effective lateral electromagnetic shields for semiconductor devices packaged in the cavities and therefore is suitable for multi-chip package with minimized internal electromagnetic interference (EMI). Accordingly, the present invention provides a multi-cavity wiring board that includes a coreless substrate, an adhesive, and a stiffener having a plurality of apertures with lateral shielding sidewalls.
In a preferred embodiment, the stiffener includes multiple apertures with electrically conductive sidewalls and is affixed on the coreless substrate using the adhesive that contacts and is sandwiched between the stiffener and the coreless substrate. The stiffener can extend to peripheral edges of the wiring board and provide mechanical support to suppress warp and bend of the wiring board. The stiffener can be a single or multi-layer structure with embedded single-level conductive traces or multi-level conductive traces, such as multi-layer circuit board. The stiffener can be made of nonmetallic materials, such as various inorganic or organic insulating materials including ceramics, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), silicon (Si), glass, laminated epoxy, polyamide or copper-clad laminate. By a plating process, the apertures of the nonmetallic stiffener can be formed with metallized sidewalls that can serve as lateral EMI shields for semiconductor devices within the apertures. The stiffener can also be made of metal, such as copper (Cu), aluminum (Al), stainless steel, etc.
The coreless substrate covers the stiffener in the first vertical direction and includes electrical pads and a build-up circuitry. The electrical pads are aligned with and exposed from the apertures of the stiffener in the second vertical direction. The build-up circuitry covers the electrical pads and the stiffener in the first vertical direction and is electrically connected to the electrical pads through first conductive vias. The build-up circuitry can include a first dielectric layer, first via openings and one or more first conductive traces. For instance, the first dielectric layer covers the electrical pads and the stiffener in the first vertical direction and can extend to peripheral edges of the wiring board, and the first conductive traces extend from the first dielectric layer in the first vertical direction. The first via openings in the first dielectric layer are aligned with the electrical pads. One or more first conductive traces extend from the first dielectric layer in the first vertical direction, extend laterally on the first dielectric layer, and extend through the first via openings in the second vertical direction to form the first conductive vias in electrical contact with the electrical pads, thereby providing signal routing for the electrical pads through the first conductive vias. Further, the build-up circuitry can provide an electrical connection between the stiffener and a portion of the electrical pads for ground connection purpose. For instance, the first conductive traces can extend into additional first via openings of the first dielectric layer in the second vertical direction to form one or more additional first conductive vias in electrical contact with a metallized first surface of the stiffener that faces the first vertical direction. The metal layer at the first surface of the stiffener is adjacent to and electrically connected to the metal layer of the metallized apertures. Accordingly, the stiffener can be electrically connected to the build-up circuitry through the additional first conductive vias, and the first conductive traces can provide an electrical connection between the lateral shielding sidewalls of the stiffener and a portion of the electrical pads for ground connection. Alternatively, one or more plated through holes can extend through the stiffener to provide an electrical connection between the stiffener and the build-up circuitry. For instance, the plated though hole at a first end can extend to and be electrically connected to an outer or inner conductive layer of the build-up circuitry and at a second end can extend to and be electrically connected to a metallized second surface of the stiffener that faces the second vertical direction. The metal layer at the second surface of the stiffener is adjacent to and electrically connected to the metal layer of the metallized apertures. As a result, the ground connection for the lateral shielding sidewalls can be provided by the plated through hole and the conductive traces of the build-up circuitry. In any case, the electrical connection between the electrical pad and the lateral shielding sidewalls of the stiffener can provided by the build-up circuitry and is favorable for effective lateral EMI shielding effect.
The build-up circuitry can include additional layers of dielectric, additional layers of via openings, and additional layers of conductive traces if needed for further signal routing. For instance, the build-up circuitry can further include a second dielectric layer, one or more second via openings and one or more second conductive traces. The second dielectric layer with one or more second via openings extends from the first dielectric layer and the first conductive traces in the first vertical direction and extends to peripheral edges of the wiring board. The second via openings are disposed adjacent to the first conductive traces. One or more second conductive traces extend from the second dielectric layer in the first vertical direction and extend laterally on the second dielectric layer and extend into the second via openings in the second vertical direction to provide electrical connections for the first conductive traces. The first via openings and the second via openings can have the same size, and the first dielectric layer, the first conductive traces, the second dielectric layer and the second conductive traces can have flat elongated surfaces that face in the first vertical direction.
The outmost conductive traces of the build-up circuitries can include one or more terminal pads to provide electrical contacts for an electronic device such as a semiconductor chip, a plastic package or another semiconductor assembly. The terminal pads can include an exposed contact surface that faces in the first vertical direction. As a result, the wiring board can include electrical contacts (i.e. the terminal pads and the electrical pads) that are electrically connected to one another and located on opposite surfaces that face in opposite vertical directions, so that the wiring board is stackable and electronic devices can be electrically connected to the wiring board using a wide variety of connection media including wire bonding or solder bumps as the electrical contacts.
The coreless substrate of the wiring board can further include one or more thermal paddles that are covered by the build-up circuitry in the first vertical direction and are exposed from the corresponding apertures of the stiffener in the second vertical direction. The thermal paddle can be made of any thermal conductive material, such as a metal layer that extends from the build-up circuitry in the second vertical direction. The build-up circuitry can further include one or more additional first conductive vias that directly contact the thermal paddle. As a result, the heat generated by a semiconductor device mounted on the thermal paddle can be dissipated through the thermal conduction pathway of the wiring board that is provided by the thermal paddle and the conductive vias formed in the build-up circuitry. Further, the thermal paddle and the above-mentioned electrical pads can be simultaneously formed and be coplanar with one another in the first and second vertical directions.
The coreless substrate can further include a placement guide for the stiffener. The placement guide extends from the build-up circuitry in the second vertical direction and is laterally aligned with the stiffener to stop undesired displacement of the stiffener. Specifically, the placement guide can laterally extend beyond and be close proximity to the peripheral edges of the stiffener. Alternatively, the placement guide can laterally extend within the aperture and be close proximity to the aperture sidewalls of the stiffener. Likewise, the coreless substrate can further include a stopper on each thermal paddle which extends from the thermal paddle in the second vertical direction and can serve as a placement guide for a semiconductor device mounted on the thermal paddle. The placement guide and the stopper can be made of a metal, a photosensitive plastic material or non-photosensitive material, such as copper, aluminum, nickel, iron, tin, alloys, epoxy or polyimide. Further, the placement guide, the thermal paddle and the electrical pads can be simultaneously formed and be coplanar with one another in the first and second vertical directions.
The placement guide and the stopper preferably have a thickness in a range of 10-200 microns, and respectively have patterns against undesirable movement of the stiffener and the semiconductor device. For instance, the placement guide and the stopper can respectively include a continuous or discontinuous strip or an array of posts. Specifically, the placement guide can be laterally aligned with four outer peripheral edges of the stiffener or four aperture sidewalk of the stiffener to stop the lateral displacement of the stiffener. For instance, the placement guide can be aligned along and conform to four sides, two diagonal corners or four corners of the outer peripheral edges of the stiffener, and a gap in between the outer peripheral edges of the stiffener and the placement guide preferably is in a range of about 0.001 to 1 mm. Alternatively, the placement guide can be aligned along and conform to four sides, two diagonal corners or four corners of the aperture edges of the stiffener, and a gap in between the aperture sidewall of the stiffener and the placement guide preferably is in a range of about 0.001 to 1 mm. Likewise, the stopper can be designed with the same concept for the above-mentioned placement guide. For instance, the stopper can conform to four sides, two diagonal corners or four corners of a semiconductor device to be mounted on the thermal paddle. Accordingly, the semiconductor device can be precisely mounted on the thermal paddle at a predetermined location by the stopper that laterally extends beyond and is laterally aligned with and close proximity to the peripheral edges of the semiconductor device. The gap in between the stopper and the semiconductor device preferably is in a range of about 0.001 to 1 mm.
The multi-cavity wiring board of the present invention can further include an interposer that extends into the aperture of the stiffener and is electrically connected to the coreless substrate. The interposer can be a silicon, glass or ceramic interposer and includes one or more first contact pads and one or more second contact pads on two opposite surfaces thereof. The first contact pads of the interposer faces the first vertical direction and can be electrically coupled to the electrical pads using a wide variety of connection media including gold or solder bumps. The second contact pads of the interposer faces the second vertical direction and can be exposed from the aperture of the stiffener. Besides, the interposer can further include one or more connecting elements (such as through vias) that electrically connect the first contact pads and the second contact pads. As a result, the second contact pads of the interposer and the terminal pads of the build-up circuitry can be electrically connected to one another and can serve as electrical contacts located on opposite surfaces of the wring board.
The present invention also provides a semiconductor assembly in which semiconductor devices such as chips extend within the apertures of the stiffener and are electrically connected to the coreless substrate. Specifically, the semiconductor device can be flip mounted on the coreless substrate or the interposer within the aperture by solder bumps on the electrical pads of the coreless substrate or the second contact pads of the interposer. Alternatively, the semiconductor device may be mounted on the thermal paddle and electrically connected to the electrical pads by wire bonds. Accordingly, the signal contact pads of the semiconductor device can be electrically connected to the signal transduction pathways of the wiring board by signal electrical pads. The ground contact pads of the semiconductor device can be electrically connected to the lateral shielding sidewalls of the stiffener by ground electrical pads. Further, the semiconductor devices located within different apertures of the stiffener can be completely enclosed by the lateral shielding sidewalls of the stiffener in the lateral directions and be spaced from one another by the stiffener. As a result, each semiconductor device can be shielded from electromagnetic interference signals from others by the metal layer of the aperture sidewalls that completely covers peripheral edges of the semiconductor device in the lateral directions.
The present invention has numerous advantages. The stiffener can provide a mechanical support for the coreless substrate. The lateral shielding sidewalls of the stiffener can serve as lateral EMI shields for semiconductor devices within the apertures and therefore are favorable for multi-chip package with minimized internal electromagnetic interference. The electrical connection between ground electrical pads and the lateral shielding sidewalls pan be provided by the build-up circuitry, and thus effective lateral electromagnetic shielding effect can diminish the internal electromagnetic interference among semiconductor devices packaged in the wiring board. The signal routing can be provided by the build-up circuitry and is advantageous for high I/O and high performance applications due to the high routing capability of the build-up circuitry. Further, the placement location of the stiffener can be accurately confined by the placement guide to avoid the undesired lateral displacement of the stiffener, thereby improving the manufacturing yield greatly. The wiring board and the semiconductor assembly using the same are reliable, inexpensive and well-suited for high volume manufacture. These and other features and advantages of the present invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.
The following detailed description of the preferred embodiments of the present invention can best be understood when read in conjunction with the following drawings, in which:
Hereafter, examples will be provided to illustrate the embodiments of the present invention. Other advantages and effects of the invention will become more apparent from the disclosure of the present invention. It should be noted that these accompanying figures are simplified. The quantity, shape and size of components shown in the figures may be modified according to practically conditions, and the arrangement of components may be more complex. Other various aspects also may be practiced or applied in the invention, and various modifications and variations can be made without departing from the spirit of the invention based on various concepts and applications.
As shown in
First dielectric layer 21 typically is made of epoxy resin, glass-epoxy, polyimide and the like and has a thickness of 50 microns. In this embodiment, first dielectric layer 211 is sandwiched between metal layer 11 and support plate 23. However, support plate 23 may be omitted in some embodiments. Support plate 23 typically is made of copper, but copper alloys or other materials are also doable. The thickness of support plate 23 can range from 25 to 1000 microns, and preferably ranges from 35 to 100 microns in consideration of process and cost. In this embodiment, support plate 23 is illustrated as a copper plate with a thickness of 35 microns.
Referring now to
Plated layer 23′ can be deposited by numerous techniques including electroplating, electroless plating, evaporating, sputtering, and their combinations as a single layer or multiple layers. For instance, plated layer 23′ is deposited by first dipping the structure in an activator solution to render first dielectric layer 211 catalytic to electroless copper, then a thin copper layer is electrolessly plated to serve as the seeding layer before a second copper layer is electroplated on the seeding layer to a desirable thickness. Alternatively, the seeding layer can be formed by sputtering a thin film such as titanium/copper before depositing the electroplated copper layer on the seeding layer. Once the desired thickness is achieved, support plate 23 and plated layer 23′ can be patterned to form first conductive traces 231 by numerous techniques including wet etching, electro-chemical etching, laser-assist etching, and their combinations with an etch mask (not shown) thereon that defines first conductive traces 231. Accordingly, first conductive traces 231 extend from first dielectric layer 211 in the downward direction, extend laterally on first dielectric layer 211 and extend into first via openings 213 in the upward direction to form first conductive vias 233 in electrical contact with electrical pads 13 and conductive layer 313 of stiffener 31.
Support plate 23 and plated layer 23′ thereon are shown as a single layer for convenience of illustration. The boundary (shown in phantom) between the metal layers may be difficult or impossible to detect since copper is plated on copper. However, the boundary between plated layer 23′ and first dielectric layer 211 is clear.
Referring now to
Second conductive traces 271 can be deposited as a conductive layer by numerous techniques including electrolytic plating, electroless plating, sputtering, and their combinations and then patterned by numerous techniques including wet etching, electro-chemical etching, laser-assist etching, and their combinations with an etch mask (not shown) thereon that defines second conductive traces 271. Preferably, first conductive traces 231 and second conductive traces 271 are the same material with the same thickness.
Accordingly, as shown in
In this embodiment, multi-cavity wiring board 200 is manufactured in a manner similar to that illustrated in Embodiment 1, except that the metallic sidewalls of apertures 311 are electrically connected to electrical pads 13 by first conductive traces 231 and plated through holes 411 that extend from conductive layer 313 on the top surface of stiffener 31 to first conductive traces 231 through stiffener 31, adhesive 15 and first dielectric layer 211 in vertical directions. Plated through holes 411 are formed by forming through holes 401 after attaching stiffener 31 and then depositing connecting layer 402 on the sidewall of through holes 401 during depositing first conductive traces 231. Through holes 401 are formed by mechanical drilling and can be formed by other techniques such as laser drilling and plasma etching with or without wet etching. In this illustration, connecting layer 402 is a hollow tube that covers the sidewall of through hole 401 in lateral directions and extends vertically to electrically connect conductive layer 313 of stiffener 31 to first conductive traces 231, and insulative filler 403 fills the remaining space in through hole 401. Alternatively, connecting layer 402 can fill through hole 401 in which case plated through hole 411 is a metal post and there is no space for an insulative filler in through hole 401.
Also shown in
For purposes of brevity, any description in above Embodiments is incorporated herein insofar as the same is applicable, and the same description need not be repeated.
Referring now to
Referring now to
Accordingly, as shown in
The wiring boards and semiconductor assemblies described above are merely exemplary. Numerous other embodiments are contemplated. In addition, the embodiments described above can be mixed-and-matched with one another and with, other embodiments depending on design and reliability considerations.
The semiconductor device can be a packaged or unpackaged chip. Furthermore, the semiconductor device can be a bare chip, or a wafer level packaged die, etc. The semiconductor devices can be mechanically and electrically connected to the coreless substrate using a wide variety of connection media including gold or solder bumps, bonding wires. Each aperture of the stiffener can be customized to accommodate a single semiconductor device. For instance, each aperture can have a square or rectangular shape with the same or similar topography and dimension as a single semiconductor device. Likewise, each thermal paddle also can be customized to have a shape with the same or similar topography as a single semiconductor device.
The term “adjacent” refers to elements that are integral (single-piece) or in contact (not spaced or separated from) with one another. For instance, the electrical pads are adjacent to the first conductive traces, but not adjacent to the second conductive traces.
The term “overlap” refers to above and extending within a periphery of an underlying element. Overlap includes extending inside and outside the periphery or residing within the periphery. For instance, in the position that the build-up circuitry faces the upward direction, the build-up circuitry overlaps the stiffener since an imaginary vertical line intersects the build-up circuitry and the stiffener, regardless of whether another element such as the adhesive is between the build-up circuitry and thestiffener and is intersected by the line, and regardless of whether another imaginary vertical line intersects the build-up circuitry but not the stiffener (within the apertures of the stiffener). Likewise, the build-up circuitry overlaps the electrical pads and the electrical pads are overlapped by the build-up circuitry. Moreover, overlap is synonymous with over and overlapped by is synonymous with under or beneath.
The term “contact” refers to direct contact. For instance, the adhesive contacts the first dielectric layer but does not contact the second dielectric layer.
The term “cover” refers to incomplete and complete coverage in a vertical and/or lateral direction. For instance, in the position that the build-up circuitry faces the upward direction, the build-up circuitry covers the stiffener in the upward direction regardless of whether another element such as the adhesive is between the stiffener and the build-up circuitry.
The term “layer” refers to patterned and un-patterned layers. For instance, the metal layer disposed on the dielectric layer can be an un-patterned blanket sheet before photolithography and wet etching. Furthermore, a layer can include stacked layers.
The terms “opening”, “aperture” and “hole” refer to a through hole and are synonymous. For instance, in the position that the build-up circuitry faces the downward direction, the electrical, pads are exposed by the apertures of the stiffener in the upward direction.
The phrase “aligned with” refers to relative position between elements regardless of whether elements are spaced from or adjacent to one another or one element is inserted into and extends into the other element. For instance, the placement guide is laterally aligned with the stiffener since an imaginary horizontal line intersects the placement guide and the stiffener, regardless of whether another element is between the placement guide and the stiffener and is intersected by the line, and regardless of whether another imaginary horizontal line intersects the stiffener but not the placement guide or intersects the placement guide but not the stiffener. Likewise, the first via openings are aligned with the electrical pads, and the electrical pads are aligned with the apertures.
The phrase “in close proximity to” refers to a gap between elements not being wider than the maximum acceptable limit. As known in the art, when the gap between the stiffener and the placement guide is not narrow enough, the location error of the stiffener due to the lateral displacement of the stiffener within the gap may exceed the maximum acceptable error limit. In some cases, once the location error of the stiffener goes beyond the maximum limit, it is impossible to align the predetermined portion of the stiffener with a laser beam, resulting in the electrical connection failure between the stiffener and the build-up circuitry. According to the dimension of the predetermined connection portion of the stiffener, those skilled in the art can ascertain the maximum acceptable limit for a gap between the stiffener and the placement guide through trial and error to ensure the conductive vias being aligned with the predetermined connection portion of the stiffener. Thereby, the descriptions “the placement guide is in close proximity to the peripheral edges of the stiffener”, “the placement guide is in close proximity to the aperture sidewalls of the stiffener” and “the stopper is in close proximity to the peripheral edges of the semiconductor device” mean that the gap between them is narrow enough to prevent the location error of the stiffener or the semiconductor device from exceeding the maximum acceptable error limit.
The phrase “mounted on” includes contact and non-contact with a single or multiple support element(s). For instance, the semiconductor devices are mounted on the thermal paddles regardless of whether they contact the thermal paddles or are separated from the thermal paddles by an adhesive.
The phrase “electrical connection” or “electrically connects” or “electrically connected” refers to direct and indirect electrical connection. For instance, the first conductive trace provides an electrical connection between the terminal pad and the electrical pads regardless of whether the first conductive trace is adjacent to the terminal pad or electrically connected to the terminal pad by the second conductive trace.
The term “above” refers to upward extension and includes adjacent and non-adjacent elements as well as overlapping and non-overlapping elements. For instance, in the position that the build-up circuitry faces the downward direction, the placement guide extends above, is adjacent to and protrudes from the first dielectric layer.
The term “below” refers to downward extension and includes adjacent and non-adjacent elements as well as overlapping and non-overlapping elements. For instance, in the position that the build-up circuitry faces the downward direction, the build-up circuitry extends below the stiffener in the downward direction regardless of whether the build-up circuitry is adjacent to the stiffener.
The “first vertical direction” and “second vertical direction” do not depend on the orientation of the wiring board, as will be readily apparent to those skilled in the art. For, instance, the build-up circuitry covers the stiffener in the first vertical direction and the electrical pads are exposed from the apertures in the second vertical direction regardless of whether the wiring board is inverted. Likewise, the placement guide is “laterally” aligned with the stiffener in a lateral plane regardless of whether the wiring board is inverted, rotated or slanted. Thus, the first and second vertical directions are opposite one another and orthogonal to the lateral directions, and a lateral plane orthogonal to the first and second vertical directions intersects laterally aligned elements. Furthermore, the first vertical direction is the downward direction and the second vertical direction is the upward direction in the position that the build-up circuitry faces the downward direction, and the first vertical direction is the upward direction and the second vertical direction is the downward direction in the position that the build-up circuitry faces the upward direction.
The wiring board and the semiconductor assembly using the same according to the present invention have numerous advantages. The wiring board and the semiconductor assembly are reliable, inexpensive and well-suited for high volume manufacture. The lateral shielding sidewalls of the stiffener can serve as lateral EMI shields for semiconductor devices within the apertures and therefore are favorable for multi-chip package with minimized internal electromagnetic interference. The signal routing provided by the build-up circuitry is advantageous for high I/O and high performance applications due to the high routing capability of the build-up circuitry. The stiffener can provide a mechanical support for the coreless substrate and electronic devices packaged in the wiring board. The placement location of the stiffener can be accurately confined by the placement guide to avoid the undesired lateral displacement of the stiffener, thereby improving the manufacturing yield greatly. The wiring board and the semiconductor assembly using the same are reliable, inexpensive and well-suited for high volume manufacture.
The manufacturing process is highly versatile and permits a wide variety of mature electrical and mechanical connection technologies to be used in a unique and improved manner. The manufacturing process can also be performed without expensive tooling. As a result, the manufacturing process significantly enhances throughput, yield, performance and cost effectiveness compared to conventional techniques.
The embodiments described herein are exemplary and may simplify or omit elements or steps well-known to those skilled in the art to prevent obscuring the present invention. Likewise, the drawings may omit duplicative or unnecessary elements and reference labels to improve clarity.
Various changes and modifications to the embodiments described herein will be apparent to those skilled in the art. For instance, the materials, dimensions, shapes, sizes, steps and arrangement of steps described above are merely exemplary. Such changes, modifications and equivalents may be made without departing from the spirit and scope of the present invention as defined in the appended claims.
Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.
This application is a continuation-in-part of U.S. application Ser. No. 13/615,819 filed Sep. 14, 2012, a continuation-in-part of U.S. application Ser. No. 13/753,625 filed Jan. 30, 2013 and a continuation-in-part of U.S. application Ser. No. 13/733,226 filed Jan. 3, 2013, each of which is incorporated by reference. This application also claims the benefit of filing date of U.S. Provisional Application Ser. No. 61/731,564 filed Nov. 30, 2012. U.S. application Ser. No. 13/753,625 filed Jan. 30, 2013 is a continuation-in-part of U.S. application Ser. No. 13/615,819 filed Sep. 14, 2012. U.S. application Ser. No. 13/615,819 filed Sep. 14, 2012, U.S. application Ser. No. 13/753,625 filed Jan. 30, 2013 and U.S. application Ser. No. 13/733,226 filed Jan. 3, 2013 all claim the benefit of filing date of U.S. Provisional Application Ser. No. 61/682,801 filed Aug. 14, 2012.
| Number | Date | Country | |
|---|---|---|---|
| 61731564 | Nov 2012 | US | |
| 61682801 | Aug 2012 | US | |
| 61682801 | Aug 2012 | US | |
| 61682801 | Aug 2012 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13615819 | Sep 2012 | US |
| Child | 13962991 | US | |
| Parent | 13753625 | Jan 2013 | US |
| Child | 13615819 | US | |
| Parent | 13733226 | Jan 2013 | US |
| Child | 13753625 | US | |
| Parent | 13615819 | Sep 2012 | US |
| Child | 13753625 | US |
