This disclosure is related to wafer level chip scale packaging, and more particularly, to wafer level chip scale packaging which will support high current.
Packaging of an integrated circuit is needed to protect the semiconductor, chip, die, or integrated circuit from physical damage. For example, damage could occur while connecting the chip to the application printed circuit board (PCB) or during its usage by the customer.
There exist several different packaging types on the market, for example, lead frame packages, ball grid array packages, chip scale packages, wafer level chip scale packages, etc. Among these, a wafer level chip scale package (WLCSP) has the smallest form factor (i.e. package size is the same as the die size) and good electrical, mechanical and thermal characteristics. It also has a simpler stackup than other package types. The assembly processing cost is also lower compared to some of the other packaging solutions.
Refer to
For the standard solder ball pitch and solder ball dimensions used by the industry for the wafer level chip scale package (WLCSP), there is a limit to the current that can be passed through the solder balls. At this time, most high power application integrated circuits using WLCSP packaging technology are carrying around 1.2 to 1.5 A per solder ball. For future products, the current per package solder pin requirement might be even more. This trend of increasing the current per solder ball in WLCSPs will only increase in the future. The current per solder ball is limited by the solder ball diameter and the size of under ball metallization (UBM) underneath the solder ball.
Moreover, in the future, the industry will be moving toward WLCSP packages with smaller solder ball diameters and pitches. It will be desirable to have as many solder balls as possible without having to increase the chip area. Reducing the size of the solder balls is desirable because larger solder ball diameters for smaller pitches have had issues such as solder ball bridging. Reducing the solder-ball pitch and hence solder ball diameter/UBM diameter will limit the current per solder ball in WLCSP even more. As solder ball dimensions and solder ball pitch are reduced in the future, it will be even more difficult to pass high amounts of current through the packaging pins (here, solder balls for wafer level chip scale package). Reducing the solder ball pitch and solder ball diameter/UBM diameter will result in reduced board level reliability and reduced thermal and electrical performance.
To solve these problems, some practitioners have tried to increase the RDL/UBM thickness or change the material properties of either RDL or UBM. Some have tried to remove the RDL all together, connecting the solder ball to the UBM or to remove the UBM all together, connecting the solder ball to the RDL. However, changing the thickness of the RDL/UBM will result in degradation of board level reliability of the package and will not be able to achieve the large amounts of current needed in the industry.
U.S. Pat. No. 9,369,175 (Lee et al), U.S. Pat. No. 6,930,032 (Sarihan et al), and U.S. Pat. No. 8,836,094 (Lin et al) and U.S. Patent Applications 2015/0187745 (Chiu et al) and 2010/0038803 (Lee et al) disclose solder plating methods in chip scale packaging.
It is the primary objective of the present disclosure to provide a chip scale package for high current application devices.
It is a further objective of the present disclosure to provide a chip scale package for high current application devices that will prevent electro-migration and fusing or melting of the package metal distribution layer and/or Under block Metallization (UBM) and/or Solder inter-connect when high currents are passed through them and thereby improve the reliability of the integrated circuit.
In accordance with the objectives of the present disclosure, a multi-pin wafer level chip scale package is achieved. One or more solder pillars (SP) and one or more solder blocks (SB) are formed on a silicon wafer wherein the one or more solder pillars (SP) and the one or more solder blocks (SB) all have a top surface in a same horizontal plane. A pillar metal layer [Under Pillar Metal (UPM)] underlies the one or more SPs and electrically connects the one or more SPs with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer [Under Block Metal (UBM)] underlies the one or more SBs and electrically connects the one or more SBs with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer (UBM) is thicker than the pillar metal layer (UPM).
Also in accordance with the objectives of the present disclosure, a method of forming a multi-pin wafer level chip scale package is achieved. A silicon wafer is provided having a passivation layer thereon having openings therein to silicon pads on the silicon wafer. A first polymer layer is coated on the passivation layer. A metal trace (Redistribution Layer [RDL]) is formed contacting silicon pads through openings in the first polymer layer in areas where low current connections are to be made and a metal block (Redistribution Layer [RDL_VIA]) is formed over and through vias contacting the silicon pads through openings in the first polymer layer in areas where high current connections are to be made wherein the metal block (RDL_VIA) is thicker than the metal trace (RDL). A solder pillar (SP) is formed on each metal trace (RDL) and a solder block (SB) is formed on each metal block (RDL_VIA) wherein the SBs are wider than the SPs and wherein a top surface of each of the SPs and SBs are in the same horizontal plane.
The primary technical objective to be achieved is a chip scale package for high current applications in which thicker Redistribution layer (RDL_VIA), a thicker and wider Under Block Metal (UBM), and wider SB will prevent electro-migration at the UBM/solder block interface and fusing of package conductor layers (UBM or RDL_VIA or Solder Block). Further technical objectives include:
In the accompanying drawings forming a material part of this description, there is shown:
The present disclosure presents chip scale packaging technology (WLCSP) having different material stackup and different package pins to support the future demands of the semiconductor industry in a far better way than the existing chip scale packaging technology.
The wafer level packaging metal layer 22a and 22b (Under Pillar and Under Block Metal) have differing thicknesses and/or widths correlated with expected current density. That is, pins 24a (solder pillars) for low current units will have thinner and narrower underlying metal layer 22a (Under Pillar Metal) while pins 24b (solder blocks) for high current units will have thicker and wider underlying metal layer 22b (Under Block Metal). Low current is considered to be less than or equal to about 2 amperes (A) while high current is greater than about 2 A.
The wafer level packaging metal layer 18a and 18b (RDL traces and RDL_VIAs) have differing thicknesses and/or widths correlated with expected current density. That is, metal layer carrying low currents, 22a (Under Pillar Metal) is connected to silicon pads through thinner and narrower underlying metal distribution layer 18a (RDL traces), while high current carrying metal layer 22b (Under Block Metal) is connected to silicon pads through thicker and wider underlying metal layer 18b (RDL_VIA).
The thicker/wider Under Block Metal (UBM) 22b connected to solder block (SB) 24b and the relatively thinner/narrower Under Pillar Metal (UPM) 22a connected to Solder Pillars (SP) 24a allows for multiple solder inter-connects for packaging. There are no point contacts as would be the case with a solder ball, but the flat cylindrical or pillar shaped solder contact 24b provides a large contact area. The solder blocks 24b are plated, not bumped. The remaining solder interconnects 24a are also non-spheres. They are cylindrical or pillar shaped and plated, not bumped.
The multi-pin WLCSP of the present disclosure provides better thermal, electrical, mechanical, and board level performance than the existing WLSCP packaging. It supports a higher current and provides a better package life and quality when supporting high DC current than the existing packages. Standard industry packaging design rules are followed by the disclosed multi-pin WLCSP.
In standard WLCSP (Prior Art
Table 1 (below) compares the maximum DC current values per packaging pin at three different temperatures for the typical WLCSP (column 2) and the MP-WLCSP of the present disclosure (column 3). Maximum current values for WLCSP are taken from the EM study done by an assembly supplier on a package having a 250 μm solder ball (24), 245 μm UBM (22) diameter, and 8.3 μm UBM (22) thickness. The maximum DC current values for MP-WLSCP are calculated values, given a solder block (24b) width of 1200 μm, UBM (22b) thickness of 50 μm and UBM (22b) width of about 1200 μm.
As shown in Table 2, an electrical simulation was run on high power blocks designed using WLCSP (column 2) and MP-WLCSP (column 3) stackup schemes. In WLCSP (
In some of the WLCSP packages, some manufacturing rules are compromised (violated) in order to achieve lower parasitic values, to improve the current density, and to reduce the chip size. Such violations might result in reducing the board level reliability of the chip scale packages. In MP-WLCSP, the new stack up dimensions and thicknesses help us achieve very good electrical performance without having to compromise or violate the critical chip scale packaging rules, hence making it more robust with respect to board level reliability and mechanical performance. Some of the important manufacturing rules that are not violated by the MP-WLCSP of the present disclosure include no silicon pads (12) under the Under Block Metal (22b) and Under Pillar Metal (22a), a minimum silicon pad size (12) of 42 μm, and an Under Block Metal (22b) and Under Pillar Metal (22a) density of greater than 25% for a chip size greater than or equal to 5×5 mm2.
Referring now more particularly to
Now, referring to
In
Next, as shown in
Now, photo resist PR3 (29) is coated and developed on top of the seed layer, as shown in
After removing the photo resist PR2 (27) and PR3 (29) and etching the unwanted RDL_VIA seed layer, the desired RDL_VIA 18b is left over. This is illustrated in
Next, as shown in
Referring now to
As illustrated in
Now, as shown in
As shown in
Next, the high current area pins are to be formed. As shown in
Now, another photo resist layer PR6 (35) is coated and developed as shown in
Now, as shown in
As shown in
It is important that both the solder pillar 24a and solder block 24b are plated to the same final level so that both end up in the same horizontal plane. The final thickness of the solder pillars will be greater than about 120 μm and the final thickness of the solder blocks will be greater than about 100 μm.
The solder pillars 24a and blocks 24b may have a flat or a curved top surface.
Referring now to
Now, as illustrated in
Next, as shown in
Referring now to
Referring now to
Now, as shown in
The PR3 29 is stripped and the UPM seed layer not covered by the solder pillar 24a is etched away, as shown in
Next, the high current area pins are to be formed. As shown in
Now, a UBM strip 22b is placed within the PR4 openings, as shown in
Returning to
It is important that both the solder pillar 24a and solder block 24b are plated to the same final level so that both end up in the same horizontal plane. The final thickness of the solder pillars will be greater than about 120 μm and the final thickness of the solder blocks will be greater than about 100 μm.
A third preferred embodiment of the present disclosure is described with reference to
A first photo resist layer PR1 (25) is coated and developed according to the pattern for the RDL trace, shown in
The PR1 25 is stripped and a new photo resist PR2 27 is formed leaving openings in both the low and high current areas. Copper, or other metal, is plated on the seed layer exposed by mask 27 in a thick uniform plating process, as shown in
The photoresist mask 27 is stripped and another mask PR3 29 is formed to expose only the low current area. The RDL plated layer is etched back to reduce the Cu thickness in the low current area 18a, as shown in
Next, as shown in
The thickness of the final RDL_trace 18a is >=4 μm and <=25 μm. The thickness of the final RDL_VIA 18b is >=25 μm and <=50 μm.
Referring now to
Referring now to
A photo resist PR4 (31) is coated and developed over the UBM layer 22 having openings where the low current carrying pins will be formed, as shown in
PR4 31 is stripped and a new mask PR5 33 is formed having openings where both high and low current carrying pins are to be formed. Thick uniform metal for UPM and UBM 22b is plated in a thick uniform process in the openings, as shown in
The PR5 33 is stripped and another mask PR6 35 is formed with an opening only over the low current areas. The UPM layer 22b is etched back, as shown in
PR6 35 is stripped and new mask PR7 37 is formed on seed layer 22 with openings where the pins are to be formed. As shown in
Finally, the PR7 37 is removed and the metal 22 not covered by the solder is etched away to complete the package, as shown in
The multi-pin WLCSP of the present disclosure provides better thermal, electrical, mechanical, and board level performance than the traditional wafer level chip scale packaging. This package supports higher current coming from analog blocks and has better quality package life when supporting high DC current for a longer time as compared to the WLCSP. The MP-WLCSP exhibits better electrical performance without having to violate any of the package design rules. Process flow, form factor, and assembly processing cost are similar to the traditional WLCSP.
Several alternatives or modifications may be made to the MP-WLCSP of the disclosure.
Although the preferred embodiment of the present disclosure has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the disclosure or from the scope of the appended claims.
This is a divisional application of U.S. Ser. No. 16/995,697, filed on Aug. 17, 2020, which is a divisional application of U.S. Ser. No. 15/686,484 filed on Aug. 25, 2017, now issued as U.S. Pat. No. 10,797,012, both assigned to the same assignee as the instant application, and which are herein incorporated by reference in their entirety.
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Number | Date | Country | |
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20230077469 A1 | Mar 2023 | US |
Number | Date | Country | |
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Parent | 16995697 | Aug 2020 | US |
Child | 17967472 | US | |
Parent | 15686484 | Aug 2017 | US |
Child | 16995697 | US |