Package-on-package (PoP) is becoming an increasingly popular integrated circuit packaging technique because PoP allows for higher density electronics.
In a conventional package-on-package process, a first package component such as an interposer is mounted onto a second package component such as a package substrate. A semiconductor chip may be mounted on the interposer using flip-chip bonding. An underfill may be dispensed into the gap between the semiconductor chip and the interposer to prevent cracks from being formed in solder bumps or solder balls. Cracks are typically caused by thermal stress and warpage. The thermal stress and warpage are caused by thermal expansion mismatch between the components of a package-on-package structure. Even with the use of underfills and interposers, the problem of warpage still cannot be entirely eliminated.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Various steps in the formation of package-on-package will be described with reference to
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.
It is understood that additional processes may be performed before, during, or after the blocks 4-14 shown in
c are cross-sectional views of intermediate stages in the manufacture of a package-on-package structure in accordance with various embodiments of the method 2 of
Referring to
Second package component 20 may be an interposer, and hence is alternatively referred to as interposer 20 hereinafter. In some embodiments, second package component 20 may be a wafer, a device die, a substrate, and/or the like. Interposer 20 may be composed of a semiconductor material such as silicon, germanium, or gallium arsenate and in at least one embodiment may have a thickness of about 20 microns to about 500 microns. In addition to providing electrical connection between a bottom package component and a top package component and thermal conduction, interposer 20 also provides mechanical stiffening to a resulting package. In this way, interposer 20 provides stiffness and resistance to warping that might otherwise occur as a result of thermal coefficient of expansion (CTE) mismatch between the top package component and the bottom package component.
Substrate 10 is coupled to interposer 20 by the first set of conductive elements 30. First set of conductive elements 30 may be solder balls, and hence is alternatively referred to as solder balls 30 hereinafter. Solder balls 30 formed on bond pads 40 act as the electrical connectors for bonding and electrically coupling substrate 10 to interposer 20. Although solder balls 30 are illustrated in
Next, as shown in
Referring now to
As was shown in
In another embodiment of the present disclosure, a second polymer-comprising material 50b is applied on the package-on-package structure shown in
To further enhance the package-on-package structure 5 of
In at least one embodiment as shown in
Advantages of one or more embodiments of the present disclosure may include one or more of the following.
In one or more embodiments, a package-on-package structure provides for improved mechanical strength and mechanical stiffness by the introduction of a molding compound in the package-on-package structure. It is believed that this mechanical stiffness reduces the severity of warpages resulting from, e.g., thermal expansion mismatch between the components of the resulting package.
In one or more embodiments, a package-on-package structure provides for improved warpage control by the introduction of a molding compound in the package-on-package structure.
In one or more embodiments, the manufacturing costs are reduced for manufacturing a package-on-package structure having improved mechanical strength and warpage control.
The present disclosure has described various exemplary embodiments. According to one embodiment, the present disclosure relates to a package-on-package structure comprising a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further comprises a second set of conductive elements that couples the second package component to a third package component.
According to another embodiment, the present disclosure relates to a package-on-package structure comprising a first package component coupled to a second package component by a first set of conductive elements. A first molding material is arranged between the first package component and the second package component and surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The underfill has a bottom surface that is above a top surface of the first molding material.
According to yet another embodiment, the present disclosure relates to a package-on-package structure comprising a first package component and a second package component. A first set of conductive elements couples the first package component to the second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements. The stacked integrated chip structure further comprises a third package component. A second set of conductive elements couples the second package component to the third package component. A second molding material is arranged on the second package component and a top surface of the first molding material. The second molding material has a top surface that is below a top surface of the third package component.
In the preceding detailed description, specific exemplary embodiments have been described. It will, however, be apparent to a person of ordinary skill in the art that various modifications, structures, processes, and changes may be made thereto without departing from the broader spirit and scope of the present disclosure. The specification and drawings are, accordingly, to be regarded as illustrative and not restrictive. It is understood that embodiments of the present disclosure are capable of using various other combinations and environments and are capable of changes or modifications within the scope of the claims.
This Application is a Continuation of U.S. patent application Ser. No. 15/143,892 filed on May 2, 2016, which is a Continuation of U.S. patent application Ser. No. 13/539,136 filed on Jun. 29, 2012 (now U.S. Pat. No. 9,349,663 issued on May 24, 2016), the contents of which are hereby incorporated by reference in their entirety.
Number | Name | Date | Kind |
---|---|---|---|
6225704 | Sumita et al. | May 2001 | B1 |
6404062 | Taniguchi | Jun 2002 | B1 |
6448665 | Nakazawa et al. | Sep 2002 | B1 |
6548330 | Murayama et al. | Apr 2003 | B1 |
6727583 | Naka | Apr 2004 | B2 |
6774467 | Horiuchi et al. | Aug 2004 | B2 |
6794273 | Saito et al. | Sep 2004 | B2 |
6853064 | Bolken et al. | Feb 2005 | B2 |
6870248 | Shibata | Mar 2005 | B1 |
7071028 | Koike et al. | Jul 2006 | B2 |
7138706 | Arai | Nov 2006 | B2 |
7187070 | Chu et al. | Mar 2007 | B2 |
7294533 | Lebonheur | Nov 2007 | B2 |
7335994 | Klein et al. | Feb 2008 | B2 |
7339264 | Shibata | Mar 2008 | B2 |
7388294 | Klein et al. | Jun 2008 | B2 |
7432600 | Klein et al. | Oct 2008 | B2 |
7556983 | Kurita | Jul 2009 | B2 |
7622801 | Kurita | Nov 2009 | B2 |
7754534 | Saito et al. | Jul 2010 | B2 |
7777351 | Berry et al. | Aug 2010 | B1 |
7843052 | Yoo et al. | Nov 2010 | B1 |
8405228 | Huang | Mar 2013 | B2 |
8723310 | Park | May 2014 | B2 |
20020074637 | McFarland | Jun 2002 | A1 |
20030141582 | Yang et al. | Jul 2003 | A1 |
20030219969 | Saito | Nov 2003 | A1 |
20040036164 | Koike et al. | Feb 2004 | A1 |
20040150081 | Ogawa | Aug 2004 | A1 |
20040253803 | Tomono et al. | Dec 2004 | A1 |
20040262776 | Lebonheur | Dec 2004 | A1 |
20060237833 | Klein et al. | Oct 2006 | A1 |
20080251913 | Inomata | Oct 2008 | A1 |
20090152700 | Kuan et al. | Jun 2009 | A1 |
20110024888 | Pagaila et al. | Feb 2011 | A1 |
20110285007 | Chi et al. | Nov 2011 | A1 |
20120171814 | Choi et al. | Jul 2012 | A1 |
20120193779 | Lee et al. | Aug 2012 | A1 |
20120211885 | Choi | Aug 2012 | A1 |
20120267782 | Chen | Oct 2012 | A1 |
20120299197 | Kwon et al. | Nov 2012 | A1 |
20130334714 | Park | Dec 2013 | A1 |
Entry |
---|
Non-Final Office Action dated Jul. 8, 2013 for U.S. Appl. No. 13/539,136. |
Final Office Action dated Jan. 22, 2014 for U.S. Appl. No. 13/539,136. |
Non-Final Office Action dated Oct. 24, 2014 for U.S. Appl. No. 13/539,136. |
Final Office Action dated Jun. 4, 2015 for U.S. Appl. No. 13/539,136. |
Notice of Allowance dated Jan. 20, 2016 for U.S. Appl. No. 13/539,136. |
Non-Final Office Action dated Jun. 27, 2016 for U.S. Appl. No. 15/143,892. |
Notice of Allowance dated Dec. 5, 2016 for U.S. Appl. No. 15/143,892. |
Number | Date | Country | |
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20170194289 A1 | Jul 2017 | US |
Number | Date | Country | |
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Parent | 15143892 | May 2016 | US |
Child | 15461796 | US | |
Parent | 13539136 | Jun 2012 | US |
Child | 15143892 | US |