Patent Application
20100252923
1. Field of the Invention
The present invention relates to a semiconductor device which has a semiconductor chip mounted on a board, and a method of manufacturing the same.
2. Description of the Related Art
In regard to a semiconductor device which employs a BGA (Ball Grid Array) structure related to the present invention, a configuration described in JP2001-044229A (Document 1) has been known, by way of example. This BGA-based semiconductor device comprises a wiring board. The wiring board comprises a predetermined circuit formed on one surface thereof, and a semiconductor chip mounted on the one surface and with a plurality of electrode pads. On the other surface of the wiring board, in turn, a plurality of external terminals are arranged in a lattice form in correspondence to the electrode pads on the semiconductor chip. Then, the electrode pads on the semiconductor chip are electrically connected with the external terminal corresponding to the electrode pads through wires and the like of the wiring board. A sealant is formed on the one surface of the wiring board so as to cover at least the entire semiconductor chip and electric connections between the semiconductor chip and the wiring board.
Such semiconductor devices that have a conventional BGA structure are manufactured, for example, using a MAP (Mold Array Process) method, by collectively sealing a plurality of semiconductor chips disposed on a wiring board.
A semiconductor device that has the BGA structure related to the present invention comprises a semiconductor chip securely adhered on a wiring board using DAF (Die Attach Film), an adhesive or the like. Then, the semiconductor device undergoes a reflow process, where solder balls which serve as external terminals of the wiring board are melted, and is bonded to a mounting board so that the semiconductor device is mounted on the mounting board. A semiconductor device is assembled by securely adhering a semiconductor chip, a wiring board and the like which are made of a plurality of types of materials each having different coefficients of thermal expansion from one another, so that the entire semiconductor device suffers from warpage due to a rise in temperature of the semiconductor device. As a result, stress is applied to external terminals bonded on a mounting board. This stress causes the external terminals to break, the external terminals to peel off from the mounting board, and other phenomena. For this reason, the electrically connection in the connected state of the semiconductor device and the mounting board is damaged, possibly resulting in degraded reliability of the semiconductor device.
As an action taken to address the foregoing problem, JP11-087414A (Document 2), for example, proposes a structure which includes an elastic member (elastomer) sandwiched between a semiconductor chip and a wiring board in order to alleviate stress which occurs between the semiconductor chip and the wiring board.
JP10-189820A (Document 3), in turn, discloses a structure for preventing a package of a semiconductor device from cracking. In this semiconductor device, a semiconductor chip is mounted, by way of a die bond film, on a board which has a bonding sheet formed with a wiring pattern and throughholes, such that a gap is formed between the die bond film and the bonding sheet in communication with the through holes of the bonding sheet.
The inventors have recognized the following problems. The elastomer, which is used as an elastic material in the configuration of aforementioned Document 2, is a very expensive material, and therefore gives rise to a problem of an increase in the manufacturing cost of semiconductor devices.
On the other hand, in the configuration described in aforementioned Document 3, since a semiconductor chip is directly secured on a board, stress will occur due to the difference in the coefficients of thermal expansion between the semiconductor chip and the board. For this reason, reliability of the semiconductor device can undergo degradation because solder balls, which serve as external terminals, are damaged as described above.
Also, in the configuration described in Document 3, a die bond film is applied on the entire back surface of a semiconductor chip. Thus, if a void occurs between the die bond film and the semiconductor chip, the package is likely to crack during a reflow process for solder balls. Further, due to the employment of the die bond film, this configuration can cause an increase in the manufacturing cost of the semiconductor device.
Moreover, in the configuration described in Document 3, a semiconductor chip is bonded only to wiring metal laminated on a bonding sheet which forms part of the board. Therefore, in this configuration, the wiring metal can be broken because stress intensively acts on the wiring metal which is caused by the effect of thermal history in the reflow process, or by the effect of thermal cycling.
The present invention is intended to solve the problems described above.
In one embodiment, there is provided a semiconductor device that includes a semiconductor chip formed with an electrode pad on one surface thereof, a wiring board having a wiring pattern, and having one surface opposing the other surface of the semiconductor chip, a connection member for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, and an external terminal arranged on the other surface of the wiring board for electrical connection with the electrode pad through the connection member and the wiring pattern. The semiconductor device also comprises a fixing member for fixing the semiconductor chip on the one surface of the wiring board so as to form a hollow which is continuous to a portion straddling between the entirety of the other surface of the semiconductor chip and the one surface of the wiring board, and to a portion adjacent to at least one outer peripheral surface of the semiconductor chip except for the other surface of the same. Also, the wiring board includes a throughhole that communicates with the hollow.
The semiconductor device of the present invention configured as described above comprises the hollow which is continuous to a portion straddling the entirety of the other surface of the semiconductor chip and the one surface of the wiring board, and to a portion adjacent to at least one outer peripheral surface of the semiconductor chip except for the other surface of the same, thereby eliminating an area on which the entirety of the other surface of the semiconductor chip adheres to the one surface of the wiring board, and reducing the area on which the outer peripheral surfaces of the semiconductor chip, except for the other surface, adhere to the fixing member. Accordingly, no stress will occur between the other surface of the semiconductor chip and the one surface of the wiring board, and stress is alleviated if it occurs between the outer peripheral surfaces of the semiconductor chip and the one surface of the wiring board through the fixing member and between the semiconductor chip and the fixing member. Otherwise, the occurrence of warpage in a semiconductor device, that is caused by the difference in the coefficients of thermal expansion between the semiconductor chip, wiring board, and the fixing member, is prevented. Also, the hollow communicates with the throughhole of the wiring board, so that even if air within the hollow expands due to a rise in the temperature of the semiconductor device during a reflow process or a semiconductor device mounting process, the expanded air can be allowed to escape to the outside of the wiring board through the throughhole. Consequently, a crack in the package of the semiconductor device can be prevented by the expanded air within the hollow. These advantages are conducive to improvements in reliability of the semiconductor device. For reference, the “one surface,” as used in the present invention, refers to any of surfaces, and the “other surface” refers to a different surface other than the one surface.
In conclusion, according to the present invention, the reliability of the semiconductor device can be improved.
The above features and advantages of the present invention will become more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purpose.
As shown in
Also, below the other main surface of semiconductor chip 6 (hereinafter called the “back side”) as the other surface, wiring board 8 is disposed. Wiring board 8 is formed with predetermined wiring pattern 9 as conducting means. Wiring board 8 employed herein is a laminate board which is formed in the shape of a substantially rectangular plate and is made of an insulating material, for example, glass epoxy or the like. Wiring board 8 is formed with a semiconductor chip mounting area 8a on one main surface thereof (hereinafter called the “front side”) as one surface. This semiconductor chip mounting area 8a is formed with a plurality of connection pads 10 in an outer peripheral zone thereof as connections corresponding to electrode pads 7 of semiconductor chip 6 mounted on wiring board 8. A plurality of lands 11 are formed on the other main surface (hereinafter called the “back side”) of wiring board 8 as the other surface.
Electrode pads 7 of semiconductor chip 6 are connected with connection pads 10 of wiring board 8 corresponding to electrode pads 7 through wires 12 as connection members made of a conductive material, for example, Au or the like. In this way, electrode pads 7 of semiconductor chip 6 are electrically connected with lands 11 corresponding to electrode pads 7 through wiring pattern 9 on wiring board 8.
Wiring board 8 is formed with sealant 13 on the front side as a fixing member made of a thermosetting resin such as epoxy resin. Sealant 13 is formed to cover at least the front side of semiconductor chip 6 and wires 12 for electrically connecting wiring board 8 with semiconductor chip 6, respectively.
Hollow 14 is also defined to be continuous to a portion which straddles the entire back side of semiconductor chip 6 and the front side of wiring board 8 and to a portion adjacent to the entire outer peripheral surfaces of semiconductor chip 6 except for the back side. Stated another way, semiconductor chip 6 is supported within hollow 14 by a plurality of wires 12 which suspend semiconductor chip 6.
Consequently, the front side of wiring board 8 opposes the back side of semiconductor chip 6, set apart therefrom, with hollow 14 interposed therebetween. This hollow 14 serves as a stress alleviation layer for alleviating stress which can occur between semiconductor chip 6 and wiring board 8.
Specifically, hollow 14 is formed to have a portion adjacent to and parallel to the back side of semiconductor chip 6 whose size is adjusted to be equal to or larger than the area of the back side of semiconductor chip 6, as shown in
In addition, hollow 14 is formed to be continuous from the back side of semiconductor chip 6 to a portion adjacent to the entire outer peripheral surfaces of semiconductor chip 6 to define one space. Accordingly, when the temperature of semiconductor device 1 rises during mounting, hollow 14 can effectively alleviate stress which occurs between the outer peripheral surface of semiconductor chip 6 except for the back side thereof and the front side of wiring board 8 through sealant 13, and stress which occurs between semiconductor chip 6 and sealant 13.
In essence, semiconductor device 1 is configured to effectively prevent stress which acts on either semiconductor chip 6 or wiring board 8 from being transmitted to the other through the back side of semiconductor chip 6, and through the entire outer peripheral surfaces of semiconductor chip 6 except for the back side of semiconductor chip 6, by hollow 14 included in semiconductor device 1 to cover entire semiconductor chip 6.
Also, hollow 14 has a boundary with sealant 13, formed in a curved surface, without corners formed on an inner surface of sealant 13. As such, it is possible to prevent stress from concentrating on a corner of the inner surface of sealant 13, thus further improving the reliability of semiconductor device 1.
Further, throughhole 15 is formed through the area of semiconductor chip mounting area 8a of wiring board 8. Throughhole 15 is positioned at one site, for example, in a central region of semiconductor chip mounting area 8a, and is in communication with hollow 14. Stated another way, hollow 14 is formed to be continuous to the back side of wiring board 8 through throughhole 15. Because communicating throughhole 15 communicates with hollow 14, air within hollow 14 is smoothly discharged to the outside from throughhole 15 even if the temperature of semiconductor device 1 rises to cause the air to expand within hollow 14. Consequently, a crack in the semiconductor device 1 can be prevented.
Notably, throughhole 15 is only required to be in communication with hollow 14, and may therefore be formed at another position of wiring board 8. Alternatively, a plurality of throughholes 15 may be formed in another configuration. Further, throughhole 15 may vary, as required, with respect to the diameter, the shape of the opening, and the like. However, since foreign substances may possibly intrude into hollow 14 from throughhole 15, throughhole 15 can have a larger effect in preventing foreign substances from intruding into hollow 14, when it is formed to have an opening of a relatively small area, or when it is formed to bend in the middle in the depth direction.
Further, since a plurality of lands 11 are arranged in a lattice form on the back side of wiring board 8, throughhole 15 is advantageously positioned in a central region of wiring board 8, for example, at the center of semiconductor chip mounting area 8a because throughhole 15 thus positioned will not prevent routing of wiring pattern 9, and permits a larger number of connection pads 10 to be arranged on wiring board 8.
Also, a plurality of external terminals 17 are formed on lands 11 of wiring board 8. A ball made of a conductive material, for example, solder or the like is mounted on land 11 through flux, and a reflow process is performed to melt the ball so that external terminal 17 is formed on land 11 with the ball.
Also, adhesive member 18 is applied to a region on the front side of wiring board 8 except for throughhole 15 within hollow 14. Adhesive member 18 employed herein is a material which keeps a predetermined adhesive strength, for example, at temperatures up to approximately 160° C., and evaporates at temperatures equal to or higher than 200° C. Adhesive member 18 is made, for example, of a film material which contains cyclic olefin-based resin blended with epoxy-based resin so as to achieve predetermined characteristics. By heating adhesive member 18 to 200° C. or higher after the formation of sealant 13, adhesive member 18 is removed to the outside of wiring board 8 from throughhole 15, thereby forming hollow 14.
Semiconductor device 1 configured as described above undergoes a reflow process, when it is mounted, where external terminals 17 are melted, and as shown in
In this way, the semiconductor device according to this embodiment comprises semiconductor chip 6 having electrode pads 7 formed on the front side (one surface); wiring board 8 having wiring pattern 9 with its one surface (front side) opposing the back side (the other surface) of semiconductor chip 6; wires 12 (connection members) for electrically connecting electrode pads 7 of semiconductor chip 6 with wiring pattern 9 of wiring board 8; external terminals 17 disposed on the back side (the other surface) of wiring board 8 and electrically connected to electrode pads 7 through wires 12 (connection members) and wiring pattern 9; and sealant 13 (fixing member) for fixing semiconductor chip 6 on the front side (one surface) of wiring board 8 such that hollow 14 is formed to be continuous to a portion which straddles between the entire back side (the other surface) of semiconductor chip 6 and the front side (one surface) of wiring board 8 and to a portion which is adjacent to at least one outer peripheral surface except for the back side (the other surface) of semiconductor chip 6. Wiring board 8 also comprises throughhole 15 in communication with hollow 14.
With this configuration, the entire back side of semiconductor chip 6 is not adhered to the front side of wiring board 8, and the outer peripheral surfaces of semiconductor chip 6 except for the back side are adhered to sealant 13 with a reduced area. Consequently, no stress will occur between the back side of semiconductor chip 6 and the front side of wiring board 8, and stress will be alleviated, if they occur between the outer peripheral surfaces of semiconductor chip 6 and the front surface of wiring board 8 through sealant 13, and between semiconductor chip 6 and sealant 13. As a result, the occurrence of warpage, which is caused by the difference in the coefficients of thermal expansion between semiconductor chip 6, wiring board 8, and sealant 13, can be prevented.
Also, hollow 14 is formed to be in communication with throughhole 15 of wiring board 8. Therefore, when air within hollow 14 expands due to a rise in temperature of semiconductor device 1 in a reflow process for applying the solder balls or a reflow process for mounting semiconductor device 1, the expanded air can be allowed to escape from throughhole 15 to the outside of wiring board 8. Thus, a crack in the package of the semiconductor device caused by the expansion of air within hollow 14 can be prevented from occurring in semiconductor device 1.
According to the foregoing configuration, the reliability of semiconductor device 1 can be improved. Also, since this embodiment does not employ any expensive material such as elastomer, semiconductor device 1 can alleviate stress occurring between semiconductor chip 6 and wiring board 8 at a relatively low cost.
Also, in this embodiment, since hollow 14 borders sealant 13 with a curved boundary surface, stress can be prevented from concentrating on a corner on an inner surface of sealant 13. Thus, by applying this embodiment to semiconductor device 1, the reliability of this device can be further improved.
Particularly, when DRAM (Dynamic Random Access Memory) is employed as semiconductor chip 6, stress on semiconductor chip 6 can be reduced by the action of hollow 14, as described above, so that a deterioration of refresh characteristics in semiconductor device 1 can prevent and so that the refresh characteristics can be improved. Notably, this embodiment may also be applied, for example, to a semiconductor device which includes a sensor unit, and a semiconductor chip which includes movable features such as MEMS (Micro-Electro-Mechanical System). (Method of Manufacturing Semiconductor Device According to First Embodiment)
First, a semiconductor wafer for use in the method of manufacturing the semiconductor device is provided by forming a silicon ingot, for example, by a single-crystal pull-up method, slicing the silicon ingot into discoidal substrates, and forming a desired circuit and electrode pads 7 on the front side of a substrate through several processes such as diffusion.
Though not shown, the semiconductor wafer is transferred to a dicing unit to undergo the dicing process. In the dicing process, the semiconductor wafer is securely adhered to a UV tape that is provided with an adhesive material which characteristically exhibits adhesive strength that becomes lower when it is irradiated with ultraviolet (UV) rays. In this state, the semiconductor wafer is ground along dicing areas positioned between adjacent semiconductor chips 6, and diced into individual semiconductor chips 6 by a dicing blade which rotates at high speeds. After dicing, the UV tape is irradiated with UV rays to reduce the adhesive strength of the UV tape. In this state, semiconductor chips 6 are pushed up from below the UV tape to peel off semiconductor chips 6 from the UV tape, and semiconductor chips 6 are picked up. In this way, semiconductor chips 6 are produced, each with a plurality of electrode pads 7 formed on the front side.
Also, wiring board 8 for use in this embodiment is processed according to a MAP method, where a unit pattern is created in the following manner.
The unit pattern of wiring board 8, i.e., one wiring board 8 which forms part of semiconductor device 1, is in a substantially rectangular shape, by way of example. As shown in
Though not particularly limited, in the configuration of the board shown in
As shown in
Wiring board 8 to which adhesive member 18 has been attached is transferred to a die bonding unit to undergo the die bonding process. In the die bonding process, semiconductor chips 6 are mounted respectively in the areas of a plurality of semiconductor chip mounting areas 8a laid out in a matrix form on wiring board 8. Semiconductor chip 6 is mounted on the front side of wiring board 8 by adhering the back side of semiconductor chip 6 to adhesive member 18 attached to semiconductor chip mounting area 8a, as shown in
Subsequently, wiring board 8 mounted with semiconductor chips 6 is transferred to a wire bonding unit to undergo the wire bonding process. In the wire bonding process, electrode pads 7 of semiconductor chips 6 mounted on wiring board 8 are electrically connected with connection pads 10 disposed in the outer peripheral zone of wiring board 8, on which semiconductor chip 6 is mounted, using wires 12 which are made of a conductive material, for example, Au or the like, as shown in
In this way, all of a plurality of electrode pads 7 included in semiconductor chip 6 are wire bonded to all of a plurality of connection pads 10 included in wiring board 8, to complete the structure as shown in
After the completion of wire bonding, resulting wiring board 8 undergoes potting of the aforementioned adhesive member 18, as a covering member, onto semiconductor chip 6 mounted on semiconductor chip mounting area 8a of wiring board 8, as shown in
Next, wiring board 8 is subjected to a resin sealing process after the entire outer peripheral surfaces of semiconductor chip 6 have been covered with adhesive member 18. In the resin sealing process, a plurality of product formation areas 21 arrayed in a matrix form are collectively sealed with a thermosetting resin such as epoxy resin to form sealant 13 on the front side of wiring board 8 so as to cover at least adhesive member 18 which covers semiconductor chip 6, and wires 12, as shown in
Subsequently, wiring board 8 formed with sealant 13 is subjected to a process for forming a hollow. In the hollow forming process, wiring board 8 formed with sealant 13 is heated to temperatures equal to or higher than 200° C. to evaporate adhesive member 18, thus discharging adhesive member 18 to the outside of wiring board 8 from throughhole 15, as shown in
By thus discharging adhesive member 18 through throughhole 15, hollow 14 is formed to be continuous between the back side of semiconductor chip 6 and the front side of wiring board 8, and to the front side and side surfaces of semiconductor chip 6, which are outer peripheral surfaces of semiconductor chip 6. This hollow 14 serves as stress alleviation layer between the outer peripheral surfaces of semiconductor chip 6 and the front side of wiring board 8.
As described above, hollow 14 is defined to have a size in the direction parallel to the back side of semiconductor chip 6 equal to or larger than the area of the back side of semiconductor chip 6, allowing the entire back side of semiconductor chip 6 to be completely spaced apart from the front side of wiring board 8 by hollow 14. By thus designing hollow 14, it is possible to eliminate stress which would otherwise occur between the back side of semiconductor chip 6 and the front side of wiring board 8.
In addition, since hollow 14 is formed to cover the perimeter, i.e., entire outer peripheral surfaces of semiconductor chip 6, the outer peripheral surfaces of semiconductor chip 6 are completely spaced apart from sealant 13. By thus designing hollow 14, it is possible to prevent, without fail, stress from occurring between the outer peripheral surfaces of semiconductor chip 6 and the front side of wiring board 8, and between the outer peripheral surfaces of semiconductor chip 6 and sealant 13.
This embodiment employs material which evaporates at a predetermined temperature for adhesive member 18, such that adhesive member 18 will be fully discharged to the outside of wiring board 8 through throughhole 15, and will not remain within hollow 14. Alternatively, a material which melts at a predetermined temperature may be employed instead for adhesive member 18, in which case hollow 14 can be formed in a similar manner to the above. Further alternatively, a material which thermally contracts at a predetermined temperature may be employed for the adhesive member, in which case thermally contracted adhesive member 18 may remain, for example, on the outer peripheral surfaces of semiconductor chip 6.
Also, hollow 14 is in communication with throughhole 15 which extends through wiring board 8 from the front side to the back side. Thus, even if the temperature of semiconductor device 1 rises, air expanding within hollow 14 is smoothly discharged to the outside of wiring board 8 from throughhole 15, so that a crack in the package of semiconductor device 1 can be prevented from occurring.
Next, wiring board 8 formed with hollow 14 between semiconductor chip 6 and wiring board 8 is transferred to a soldering ball mount unit to undergo the solder ball mount process. In the ball mount process, conductive balls are mounted on a plurality of lands 11 arranged on the back side of wiring board 8 in a lattice form, as shown in
Subsequently, wiring board 8 formed with external terminals 17 is transferred to a board dicing unit to undergo the board dicing process. In the board dicing process, wiring board 8 is cut and separated along dicing lines 24, as shown in
As described above, the manufacturing method according to this embodiment comprises the steps of providing a semiconductor chip including a plurality of electrode pads 7 arranged on the front side (one surface) thereof; and providing wiring board 8 including wiring pattern 9, semiconductor chip mounting area 8a defined on the front side (one surface), throughhole 15 pierced within semiconductor chip mounting area 8a, and a plurality of lands 11 arranged on the back side (the other surface) thereof. The manufacturing method according to this embodiment also comprises the steps of securely adhering the other surface of semiconductor chip 6 to semiconductor chip mounting area 8a of wiring board 8 with adhesive member 18; electrically connecting electrode pads 7 of semiconductor chip 6 with wiring pattern 9 through wires 12 (connection members); and forming sealant 13 (fixing member) so as to fix semiconductor chip 6 covered with adhesive member 18 (covering member) on the front side (one surface) of wiring board 8. The manufacturing method according to this embodiment further comprises the steps of forming hollow 14 continuous to a portion which straddles the entire back side (the other surface) of semiconductor chip 6 and the front side (one surface) of wiring board 8 and continuous to a portion adjacent to at least one outer peripheral surface of semiconductor chip 6 except for the back side (the other surface) thereof by removing adhesive member 18, which securely adheres semiconductor chip 6 on wiring board 8, to the outside of wiring board 8 through throughhole 15, after the formation of sealant 13 (fixing member); and forming external terminals 17 on lands 11 of wiring board 8. With each of these steps, resulting semiconductor device 1 includes hollow 14 which is extended from the portion that straddles the entire back side (the other surface) of semiconductor chip 6 and the front side (one surface) of wiring board 8 to the portion adjacent to at least one outer peripheral surface of semiconductor chip 6 except for the back side (the other surface) thereof.
According to the manufacturing method of this embodiment, semiconductor device 1, having improved reliability in preventing stress from being transferred to semiconductor chips, can be manufactured at a relatively low cost by alleviating stress, that acts on semiconductor chip 6 or wiring board 8, by the action of hollow 14 without using a relatively expensive elastic material such as elastomer.
Additionally, semiconductor device 1 may comprise porous material 31 disposed within throughhole 15, as shown in
Also, in the embodiment described above, adhesive member 18 is applied over the entire back side of semiconductor chip 6, but adhesive member 18 may be formed in a rectangular frame shape along the outer peripheral edges of semiconductor chip mounting area 8a on wiring board 8, in other words, along the outer peripheral edges of the back side of semiconductor chip 6. Throughhole 15, in turn, is only required to communicate with hollow 14, and can be placed freely at a position other than the center of wiring board 8, for example, at a position at which no wiring pattern 9 exits.
Next, other embodiments will be described with reference to the drawings. In other embodiments, the same component members as those of the first embodiment are designated the same reference numerals, and descriptions thereon are omitted.
A second embodiment will be described with reference to
Semiconductor device 2 according to the second embodiment is configured substantially in a similar manner to the first embodiment, except for two throughholes 15a, 15b which are pierced through wiring board 8 at predetermined positions, as shown in
As shown in
Alternatively, the throughhole may be formed to bend in the middle in the depth direction, or formed to incline with respect to the thickness direction of wiring board 8. The throughhole thus formed can smoothly discharge evaporated or melted adhesive member 18 from hollow 14 to the outside, and prevent foreign substances from intruding from the outside into hollow 14.
Next, a third embodiment will be described with reference to
While the foregoing embodiments have been described in connection with the configuration which has one semiconductor chip 6 mounted on wiring board 8, semiconductor device 3 according to the third embodiment is configured substantially in a similar manner to the foregoing embodiments, except that two semiconductor chips are placed one on the other, as shown in
As shown in
While the present invention has been specifically described with reference to embodiments thereof, it should be understood that the present invention is not limited to the foregoing embodiments and can be modified in various manners without departing from the spirit thereof. For example, while the foregoing embodiments have been described in connection with the configuration where a plurality of electrode pads 7 are arranged in an outer peripheral zone on the front side of semiconductor chip 6, the present invention can also be applied to semiconductor chips which differ in the arrangement of electrode pads, for example, a center-pad configuration which comprises electrode pads arranged in a central area on the front side of a semiconductor chip, and the like. Also, while the embodiments have been described in connection with a semiconductor device that has BGA structure to which the present invention is applied, the present invention can also be applied to a semiconductor device that has LGA (Land Grid Array) structure.
It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-093060 | Apr 2009 | JP | national |
