BRIEF DESCRIPTIONS OF THE DRAWINGS
FIG. 1 is a plan view showing a multi-chip module according to an Embodiment 1 of the present invention through a sealing material;
FIG. 2 is a cross sectional view showing a structure of the multi-chip module according to an Embodiment 1 of the present invention cut along the line A-A in FIG. 1;
FIG. 3 is a plan view showing a structure of a back surface of the multi-chip module shown in FIG. 1;
FIG. 4 is a schematic cross sectional view showing a unit cell structure of an n-channel type vertical field effect transistor used in a high-side power MOSFET of the multi-chip module;
FIG. 5 is an outer appearance perspective view showing a structure of the multi-chip module shown in FIG. 1;
FIG. 6 is a circuit diagram showing an example of an equivalent circuit of a non-isolated DC-DC converter using the multi-chip module shown in FIG. 1;
FIG. 7 is a graph showing a relation between a parasitic inductance of a wiring DH and a switching loss;
FIG. 8 is a graph showing a relation between the parasitic inductance of the wiring DL and a loss at a time of recovery;
FIG. 9 is a graph showing a relation between the parasitic inductance of the wiring DL and a gate surge voltage of the low-side power MOSFET;
FIG. 10 is a plan view showing a multi-chip module in the case of replacing a part of a wire connection by a plate conductive member in the Embodiment 1 of the present invention, through the sealing material;
FIG. 11 is a cross sectional view showing a structure of the multi-chip module cut along the line A-A in FIG. 10;
FIG. 12 is a plan view showing a multi-chip module in the case that the low-side power MOSFET is installed close to an external connection terminal side of a ground side plate lead portion in the Embodiment 1 according to the present invention, through the sealing material;
FIG. 13 is a plan view showing a multi-chip module according to an Embodiment 2 of the present invention through a sealing material;
FIG. 14 is a plan view showing a multi-chip module according to an Embodiment 3 of the present invention through a sealing material;
FIG. 15 is a plan view showing a multi-chip module according to an Embodiment 4 of the present invention through a sealing material;
FIG. 16 is a plan view showing a multi-chip module according to an Embodiment 5 of the present invention through a sealing material;
FIG. 17 is a plan view showing a multi-chip module according to an Embodiment 6 of the present invention through a sealing material;
FIG. 18A is a schematic cross sectional view showing a unit cell structure of an n-channel type lateral field-effect transistor used in a high-side power MOSFET in the Embodiment 6 of the present invention;
FIG. 18B is a schematic cross sectional view showing a unit cell structure of the n-channel type lateral field-effect transistor used in the high-side power MOSFET in the Embodiment 6 of the present invention;
FIG. 19 is a plan view showing a multi-chip module according to an Embodiment 7 of the present invention through a sealing material;
FIG. 20 is a schematic cross sectional view showing a unit cell structure of a p-channel type vertical field effect transistor used in a high-side power MOSFET in the Embodiment 7 according to the present invention;
FIG. 21A is a schematic plan view showing an output stage n-channel type power MOSFET of a driver IC chip 30 mounted to a multi-chip module according to an Embodiment 8 of the present invention as seen from an upper surface;
FIG. 21B is a schematic cross sectional view of the output stage n-channel type power MOSFET of the driver IC chip 30 mounted to the multi-chip module according to the Embodiment 8 of the present invention cut along the line S-S′ shown in FIG. 21A;
FIG. 21C is a schematic cross sectional view of the output stage n-channel type power MOSFET of the driver IC chip 30 mounted to the multi-chip module according to the Embodiment 8 of the present invention cut along the line D-D′ shown in FIG. 21A;
FIG. 22 is a schematic plan view showing the output stage n-channel type power MOSFET shown in FIG. 21A to FIG. 21D by removing a metal wiring M3 and a metal wiring through hole TH3;
FIG. 23 is a schematic plan view showing a connection state between the output stage n-channel type power MOSFET driving a gate of the low-side power MOSFET chip 30 and an output terminal 31b on the driver IC chip 30;
FIG. 24A is a cross sectional view showing a unit cell structure of the output stage n-channel type power MOSFET shown in FIG. 21A; and
FIG. 24B is a cross sectional view showing a unit cell structure of the output stage n-channel type power MOSFET shown in FIG. 21A.
Patent Application
20070200537
