SEMICONDUCTOR DEVICE

Abstract

This invention is to provide a nonvolatile memory device that enhances a size reduction and mass productivity while ensuring reliability and signal transmission performance. A nonvolatile memory chip having a first side formed with no pads and a second side formed with pads is mounted on a mounting substrate. A control chip for controlling the nonvolatile memory chip is mounted on the nonvolatile memory chip. The control chip has a first pad row corresponding to the pads of the nonvolatile memory chip. The first pad row is mounted adjacent to the first side of the nonvolatile memory chip. The first pad row of the control chip and a first electrode row formed on the mounting substrate are connected via a first wire group. The pads of the nonvolatile memory chip and a second electrode row formed on the mounting substrate are connected via a second wire group. The first electrode row and the second electrode row are connected through wirings formed in the mounting substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing one embodiment of a nonvolatile memory device according to the present invention;

FIG. 2 is a schematic section of the nonvolatile memory device shown in FIG. 1;

FIG. 3 is a plan view illustrating another embodiment of a nonvolatile memory device according to the present invention;

FIG. 4 is a schematic section of the nonvolatile memory device shown in FIG. 3;

FIG. 5 is a plan view showing a further embodiment of a nonvolatile memory device according to the present invention;

FIG. 6 is a schematic section of the nonvolatile memory device shown in FIG. 5;

FIG. 7 is a plan view showing a still further embodiment of a nonvolatile memory device according to the present invention;

FIG. 8 is a schematic section of the nonvolatile memory device shown in FIG. 7;

FIG. 9 is a plan view showing a still further embodiment of a nonvolatile memory device according to the present invention;

FIG. 10 is a schematic section of the nonvolatile memory device shown in FIG. 9;

FIG. 11 is a plan view depicting a still further embodiment of a nonvolatile memory device according to the present invention;

FIG. 12 is a schematic section of the nonvolatile memory device shown in FIG. 11;

FIG. 13 is a plan view showing a nonvolatile memory layer of an MCP configuration discussed prior to the invention of the present application;

FIG. 14 is a plan view illustrating a nonvolatile memory layer of an MCP configuration discussed prior to the invention of the present application; and

FIG. 15 is a plan view depicting a nonvolatile memory layer of an MCP configuration discussed prior to the invention of the present application.

Claims

1. A nonvolatile memory device comprising: a mounting substrate;a nonvolatile memory chip mounted over the mounting substrate and each having a first side unformed with bonding pads; anda control chip mounted over the nonvolatile memory chip, said control chip having a second side provided with a first bonding pad row interposed between external terminals and the nonvolatile memory chip and corresponding to the external terminals and the nonvolatile memory chip and with a first bonding wire group connected thereto;wherein the second side of the control chip is disposed adjacent to the first side of the nonvolatile memory chip, and the first bonding wire group connects between the first bonding pad row and a first electrode row formed in the mounting substrate respectively, andwherein the first electrode row and a second electrode row formed corresponding to the external terminals and the nonvolatile memory chip are connected by wires formed in the mounting substrate.

2. The nonvolatile memory device according to claim 1, wherein the nonvolatile memory chip has a third side excluding the first side, which is provided with a second bonding pad row and a second bonding wire group connected thereto, and the second bonding wire group connects between the second bonding pad row and the second electrode row formed in the mounting substrate respectively.

3. The nonvolatile memory device according to claim 2, wherein the nonvolatile memory chip has a fourth side excluding the first and third sides, which is provided with a third bonding pad row and a third bonding wire group connected thereto, the third bonding wire group connects between the third bonding pad row and a third electrode row formed in the mounting substrate respectively, and the first electrode row and the third electrode row are connected by the wires.

4. The nonvolatile memory device according to claim 2, wherein the control chip has a memory management circuit including any one of a circuit for detecting and correcting an error of read data, a redundant circuit for substituting a defective portion with a spare area, and a leveling circuit for leveling the number of rewritings in memory block units.

5. The nonvolatile memory device according to claim 4, wherein the nonvolatile memory chip is formed by a first semiconductor manufacturing technique, andwherein the control chip is formed by a second semiconductor manufacturing technique different from the first semiconductor manufacturing technique.

6. The nonvolatile memory device according to claim 4, wherein the control chip is capable of being combined with a plurality of nonvolatile memory chips, andwherein the nonvolatile memory chip is mounted one or plural.