Patent Application
20130181344
1. Field of the Invention
The present invention relates to semiconductor module mounted on a device mounting board and a method for the semiconductor module.
2. Description of the Related Art
Portable electronic devices, such as mobile phones, PDAs, DVCs and DSCs, are gaining increasing sophistication in functions and features. And to be accepted by the market, they have to be smaller in size and lighter in weight, and for the realization thereof, there is a growing demand for highly-integrated system LSIs. On the other hand, these electronic devices are desired to be easier or handier to use, and therefore the LSIs used in those devices are required to be more functionally sophisticated and better performing. For this reason, the higher integration of LSI chips is causing increases in I/O count, which in turn generates demand for smaller packages. To satisfy both these requirements, it is strongly desired that semiconductor packages suited for the high board density packaging of semiconductor components be developed. To meet such needs, a variety of packaging technologies called CSP (Chip Size Package) are being developed.
As the semiconductor module is made smaller in size or miniaturized, a wiring substrate that constitutes the semiconductor module, namely the wiring substrate in the device mounting board, is getting denser and thinner. Accordingly, the occurrence of creases in a metallic sheet used to form a wiring layer in a fabrication process is likely to cause a drop in the fabrication yield. This makes it hard to handle the wiring layer during processing and also hard to handle a process performed when the device mounting board is pressed-bonded to a semiconductor device.
The present invention has been made in view of the foregoing problems to be resolved, and a purpose thereof is to provide a technology capable of making it easy to handle the component members when the semiconductor modules are manufactured and capable of simplifying the process of manufacturing the semiconductor modules.
One embodiment of the present invention relates to a method for fabricating a semiconductor module. The method for fabricating a semiconductor module includes: a process of forming a wiring layer, where a substrate electrode is provided, by selectively removing a metallic sheet held on a supporting base; and a process of forming a device mounting board, which includes the wiring layer, the substrate electrode, and an insulating resin layer, by forming the insulating resin layer on the supporting base in a manner such that a top face itself of the substrate electrode or a metallic layer disposed on the top face of the substrate electrode or is exposed, wherein, the process of forming the wiring layer includes a process where the wiring layer is formed in a tapered shape such that the end surface of the wiring layer enters inside a wiring layer forming region as the end surface thereof approaches the semiconductor device.
Embodiments will now be described by way of examples only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures in which:
Hereinbelow, the preferred embodiments will be described with reference to the accompanying drawings. Note that in all of the Figures the same reference numerals are given to the same components and the description thereof is omitted as appropriate.
The device mounting board 12 includes an insulating resin layer 20 formed of an insulating resin layer 20, a wiring layer 30 provided on one of main surfaces of the insulating resin layer 20, and a plurality of bump electrodes 32, which electrically connect to the wiring layer 30 and protrude from the wiring layer 30 toward the insulating resin layer 20.
The insulating resin layer 20 may be formed of a thermosetting resin such as a melamine derivative (e.g., BT resin), liquid-crystal polymer, epoxy resin, PPE resin, polyimide resin, fluorine resin, phenol resin or polyamide bismaleimide, or the like. From the viewpoint of improving the heat radiation of the semiconductor module 10, it is desirable that the insulating resin layer 20 has a high thermal conductivity. In this respect, it is preferable that the insulating resin layer 20 contains, as a high thermal conductive filler, silver, bismuth, copper, aluminum, magnesium, tin, zinc, or an alloy of two or more elements selected from thereamong.
The wiring layer 30, which is provided on one main surface of the insulating resin layer 20, is formed of a conducive material, preferably of a rolled metal or more preferably of a rolled copper. A plurality of bump electrodes 32 are, in a protruding manner, on an insulating resin layer 20 side. In the first embodiment, the wiring layer 30 and the bump electrode 32 are formed integrally with each other, but the present embodiment is not limited thereto.
An end surface E of the wiring layer 30 is in contact with the insulating resin layer 20. The end surface E of the wiring layer 30 is formed in a tapered shape such that the end surface E thereof enters inside a wiring layer forming region as the end surface E thereof approaches the semiconductor device 100. Different from a case of the tapered shape where the end surface E of the wiring layer 30 overhangs outward as the end surface E thereof comes close to the semiconductor device 100, the area where a solder ball 80 described later, which is an external connection electrode, is formed can be made larger if used is the shape according to the present embodiment. Thus, the external connection electrode having a large area connected to the wiring layer 30 can be formed. Since the contact area between the external connection electrode and the wiring layer is large, the heat generated from the semiconductor device can be efficiently radiated to the outside and, at the same time, the adhesion between the wiring layer and the external connection electrode can be improved.
The planar view of the bump electrode 32 is a round shape, and each bump electrode 32 has a side surface that is shaped with a diameter smaller toward a head portion. The side surface of the bump electrodes 32 may be tilted in the same direction as the tilted direction of the end surface E of the wiring layer 30. In such a case, a bottleneck (hindrance portions that hinder the radiation of heat) in a diffusion path through which the heat generated from the semiconductor device can dissipate can be eliminated, so that the heat can be efficiently radiated. Note here that the shape of the bump electrode 32 is not limited to any particular shape and may be, for instance, in the shape of a cylinder with a predetermined diameter. Also, the bump electrode 32 may be polygonal, such as quadrangular, when viewed planarly.
An Au/Ni layer 34 is provided on the top face and the side surface of the bump electrode 32. The Au/Ni layer 34 is comprised of an Au layer, which is the exposed surface of the Au/Ni layer 34, and a Ni layer, which is held between the Au layer and the top face of the bump electrode 32.
A protective layer 70 is disposed on a main surface of the wiring layer 30 opposite to the second insulating resin layer 20. The protective layer 70 protects the wiring layer 30 against oxidation or the like. The protective layer 70 may be a solder resist layer, for instance. An opening 72 is formed in a predetermined region of the protective layer 70, and the wiring layer 30 is partially exposed by the opening 72. A solder ball 80 is formed within the opening 72 as the external connection electrode. And the solder ball 80 and the wiring layer 30 are electrically connected to each other. The position in which the solder balls 80 are formed, namely a forming region of the opening 72, are targeted positions where circuit wiring is extended through a rewiring (the wiring layer 30).
The semiconductor device 100 includes a semiconductor substrate 50, device electrodes 52, Au/Ni layers 54, and a protective layer 56. The device electrode 52, the Au/Ni layer 54, and the protective layer 56 are formed on one main surface of the semiconductor substrate 50. More specifically, the semiconductor substrate 50 is a silicon substrate such as a P-type silicon substrate. A predetermined integrated circuit (not shown) and the device electrode 52 positioned in an outer periphery of the predetermined integrated circuit are formed on one main surface of the semiconductor substrate 50. The device electrode 52 is made of a metal such as aluminum or copper. The insulating-type protective layer 56 to protect the semiconductor substrate 50 is formed in a region on the main surface of the semiconductor substrate 50 excepting the device electrodes 52. The protective layer 56 to be used may be a silicon dioxide film (SiO2), a silicon nitride film (SiN) or polyimide (PI), for instance. The Au/Ni layer 54 is formed on top of the device electrode 52 such that the Au layer is an exposed surface.
Gold of the Au/Ni layer 34 provided on the top face of the bump electrode 32 and gold of the Au/Ni layer 54 provided on the surface of the device electrode 52 are Au—Au bonded to each other. Thereby, the bump electrode 32 and the element electrode 52 corresponding to this bump electrode 32 are electrically connected to each other. The structure where the Au/Ni layer 34 and the Au/Ni 54 are Au—Au bonded together contributes to an improved electric connection reliability between the bump electrode 32 and the device electrode 52 corresponding thereto.
The structure and arrangement of the semiconductor module 10 according to the present embodiment makes it easier for the insulating resin layer 20 disposed between the wiring layer 30 and the semiconductor device 100 to flow along the tapered end surface E of the wiring layer 30 when the device mounting board 12 and the semiconductor device 100 are press-bonded to each other. Thus the insulating resin layer 20 is filled into every corner of a space between the wiring layer 20 and the semiconductor device 100. As a result, the adhesion between the insulating resin layer 20 and the wiring layer 30 and the adhesion between the insulating layer 20 and the protective layer 70 can be improved.
When it is checked that the wiring wire 30 is not short-circuited using a microscope, it is only necessary to observe the wiring wire 30 by focusing on an end located far from the semiconductor device 100 in the end surface E. This can reduce the number of steps otherwise required for the checking.
(First Method for Fabricating a Semiconductor Module)
Referring to
As illustrated in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
At this stage, the wiring layers 30 have already been patterned and the semiconductor substrate 50 is visible, in an area where the wiring layers 30 are not provided, through the supporting base 300, the adhesion layer 310 and the insulating layer 20. Thus, with provision of alignment marks (not shown) on the semiconductor substrate 50, the device mounting board 12 and the semiconductor substrate 50 can be positioned while the alignment marks on a semiconductor substrate 50 side are directly observed.
Then, as shown in
With the Au/Ni layer 34 provided on the top face of the bump electrode 32 being exposed, the device mounting board 12 and the semiconductor device 100 are finally and permanently press-bonded to each other. This suppresses residues from remaining between the Au/Ni layer 34 and the Au/Ni layer 54 and therefore the electric connection reliability between the bump electrodes 32 and the device electrodes 52 can be improved.
Then, as shown in
Then, as shown in
Then, as illustrated in
Through the processes as described above, the semiconductor modules 10 according to the first embodiment are manufactured. In the above-described method for manufacturing the semiconductor module 10, the bump electrodes 32, the Au/Ni layers 34 and the wiring layers 30 are formed while the copper sheet 200 is being supported by the supporting base 300. Thus, the handling of the copper sheet 200 in these processes of forming the bump electrodes 32, the Au/Ni layers 34 and the wiring layers 30 is easier and therefore the possibility that the wiring layers 30 and the bump electrodes 32 may be damaged can be reduced. As a result, the manufacturing yield of the semiconductor modules can be improved.
When the device mounting board 12 is finally press-bonded to the semiconductor device 100, the wiring layers 30 have already been formed in the device mounting board 12 by that time and therefore no extra metallic portion available for the formation of the wiring layer 30. Thus, the warping otherwise caused when the device mounting board 12 is finally press-bonded to the semiconductor device 100 can be prevented.
Also, it is not necessary to adjust the thickness of the copper sheet 200 by etching the copper sheet 200 down to have the thickness of the wiring layer 30 before the formation of the wiring layer 30 out of the copper sheet 200. Thus the manufacturing time can be reduced and the variation in the thickness of the wiring layers 30 can be suppressed.
In this fabrication method as described above, the Au/Ni layer 34s are covered with the insulating resin layer 20 before the insulating resin layer 20 is turned into thin film and then the Au/Ni layers 34 formed on the top face of the bump electrodes 32 are exposed (see
A second method for fabricating a semiconductor module 10 is the same as the second method up to the process of
Then, as illustrated in
In this manner, the insulating resin layer 20 is replaced by the high-performance insulating resin layer 20′. Then, similar to the first method for fabricating the semiconductor module, the processes shown in
A description is now given hereunder of advantageous effects achieved by employing the second method for fabricating the semiconductor module. The end surface E of the wiring layer 30 is formed in a tapered shape such that the end surface E thereof enters inside the wiring layer forming region as the end surface E thereof gets closer to the semiconductor device 100. Also, the bump electrode 32 is of a shape such that the diameter thereof becomes smaller toward the head portion thereof. In other words, the end surface of the wiring layer 30 and the side surface of the bump electrode 32 are of a tapered shaped such that an opening section (space) surrounded by the wiring layer 30, the bump electrode 32 and the semiconductor device 100 becomes wider as this space approaches the semiconductor device 100. Accordingly, the insulating resin layer 20′ smoothly flows into the opening section when the insulating resin layer 20′ is injected thereinto. This structure and profile suppress the occurrence of the void formed between the wiring layer 30, the bump electrode 32 and the semiconductor device 100. As a result, the manufacturing yield and the operation reliability of the semiconductor modules can be improved.
Also, the content percentage of fillers in the insulating resin layer 20 used in the final press-bonding process is set to a relatively low value. Thereby, when the bump electrode 32 and the insulating resin layer 20 are bonded together through the Au—Au bonding, the possibility that the fillers in the insulating resin layer remain in the bonding interface can be reduced. Thus, the insulating resin layer 20 is replaced by the insulating resin layer 20′ whose performance is higher than that of the insulating resin layer 20 on the condition that the connection reliability between the bump electrode 32 and the device electrode 52 has been assured. Hence, the connection reliability can be improved and, at the same time, a high functionality of insulating resin layer can be achieved.
(Third Method for Fabricating a Semiconductor Module)
As illustrated in
Then, as shown in
Then, as shown in
Then, as shown in
Subsequently, the processes similar to those shown in
In the third method for fabricating a semiconductor module, the Au/Ni layers 34 also serves as the mask used to form the bump electrodes 32 out of the copper sheet 200, the process otherwise required for the formation and the removal of a mask can be omitted. This can further simplify the manufacturing process and also reduce the manufacturing time and the manufacturing cost.
(Fourth Method for Fabricating a Semiconductor Module)
The wiring layers 30 may be formed patterning the copper sheet 200 after the process shown in
In the fourth method for fabricating a semiconductor module, no bump electrodes is formed in the device mounting board 12. Thus, the thickness of the wiring layer 30 can be made equal to the thickness of the copper sheet 200. Thus the wiring layers 30 can be turned into thin film while the occurrence of warping in the semiconductor module 10 is suppressed.
The present invention is not limited to the above-described embodiments only. It is understood that various modifications such as changes in design may be made based on the knowledge of those skilled in the art, and the embodiments added with such modifications are also within the scope of the present invention.
In the above-described first and second embodiments, for example, the bump electrode 32 and the device electrode 52 are electrically connected to each other through the Au—Au bonding connection. However, a Sn (tin) plating layer may be formed, instead, on the top face of the bump electrode 32, so that the bump electrode 32 and the device electrode 52 may be electrically connected through Sn—Au connection. Or, instead of the Au/Ni layer 54, a Cu (copper) layer may be formed on top of the device electrode 52, so that the Cu layer and the bump electrode 32 may be directly bonded to each other through Cu—Cu connection. By employing such bonding methods as those described herein, the amount of Au used can be reduced and thus the manufacturing cost of the semiconductor modules can be reduced. Since Sn is a material that is easily deformable, the variation in height of the bump electrodes 32 is absorbed by the deformation of the Sn layer if the Sn plating layer is used in substitution for the Au/Ni layer. This can suppress the drop in the manufacturing yield of the semiconductor modules caused by the variation in height of the bump electrodes 32.
(Structure of Solar Cell)
A description is given hereunder of a mode of carrying out the present invention where the present embodiments are used for a solar cell or solar battery.
The passivation layer 457 is an insulating material used to prevent a defective part from touching the upper electrode 458, the collecting electrode 459 and the bus bar 460. Also, the passivation layer 457 is laminated entirely on the semiconductor layers and therefore it needs to have optical transparency not to obstruct the incident light of the sun light. Also, in consideration of an environment where it is used as a solar cell outdoors, it is required that the passivation layer 457 be excellent in weather resistance and stable against the humidity and the light. In some instances, the solar cell may be bent or given a shock, so that the passivation layer 457 should also have a certain level of mechanical strength. Such a material may be preferably a polymer resin. More specifically, the material may be polyester, ethylene-vinyl acetate copolymer, acrylate resin, epoxy resin, urethane, and so forth, for instance. The film thickness of the passivation layer 457 may be optional as long as it can keep the electric insulating property and does not fail to have optical transparency. For example, the film thickness thereof may be 3 μm to 5 μm. The upper electrode 458 carries out the same function as that of the collecting electrode 458. A material for the electrode may be, for example, a metal such as Ag, Pt, Cu, and C, or the like. The bus bar 60 is an electrode used to further collect the current flowing through the collecting electrode 459. A material for the bus bar 60 may be a metal such as Ag, Pt, and Cu. A detailed description is now given hereinbelow of a structure of a solar cell according to exemplary embodiments but the present invention is not limited by those exemplary embodiments.
(Method for Manufacturing a Solar Cell)
As shown in
In the present exemplary embodiment, the material constituting the passivation layer 557 is the same material as that constituting the above-described insulating resin layer 20 in connection with
Referring to
The features and characteristics of the present invention described based on the embodiments may be defined by the following Item 1 to Item 8:
(Item 1) A semiconductor module including:
an insulating resin layer;
a wiring layer disposed on one main surface of the insulating layer;
a bump electrode protruding on a side of the insulating resin layer from the wiring layer; and
a semiconductor device where a device electrode is disposed counter to the bump electrode,
wherein an end surface of the wiring layer is of a tapered shape such that the end surface thereof enters inside a wiring layer forming region as the end surface thereof approaches the semiconductor device, and
the bump electrode penetrates the insulating resin layer, and the bump electrode and the device electrode are electrically connected to each other.
(Item 2) A semiconductor module according to Item 1, wherein the bump electrode is tapered in the same direction as a tapered direction of the end surface of the wiring layer.
(Item 3) A method, for fabricating a semiconductor module, including:
a process of forming a wiring layer, where a substrate electrode is provided, by selectively removing a metallic sheet held on a supporting base; and
a process of forming a device mounting board, which includes the wiring layer, the substrate electrode, and an insulating resin layer, by forming the insulating resin layer on the supporting base in a manner such that a top face itself of the substrate electrode or a metallic layer disposed on the top face of the substrate electrode is exposed.
(Item 4) A method, for fabricating a semiconductor module, according to Item 3, further including, after the process of forming the device mounting board:
a process of press-bonding the device mounting board and the semiconductor device held by the supporting base in a manner such that a top face itself of the substrate electrode or a metallic layer disposed on the top face of the substrate electrode is electrically connected to a device electrode, of a semiconductor device, disposed counter to the device mounting board; and
a process of removing the supporting base.
(Item 5) A method, for fabricating a semiconductor module, according to any one of Item 2 to Item 4, wherein the process of forming the wiring layer includes a process of forming the wiring layer in a tapered shape such that an end surface of the wiring layer enters inside a wiring layer forming region as the end surface thereof approaches the semiconductor device.
(Item 6) A method, for fabricating a semiconductor module, according to any one of Item 2 to Item 5, wherein the substrate electrode is a bump electrode that is formed integrally with the wiring layer by selectively removing the metallic sheet.
(Item 7) A method, for fabricating a semiconductor module, according to any one of Item 2 to Item 6, wherein the supporting base is transparent, and
wherein, when the device mounting board is press-bonded to the semiconductor device, the device mounting board and the semiconductor device are positioned by verifying the position of the semiconductor device through the supporting base.
(Item 8) A method, for fabricating a semiconductor module, according to any one of Item 2 to Item 7, further including, after the process of press-bonding the semiconductor device to the device mounting board and the process of removing the supporting base:
a process of forming another insulating resin layer in substitution for the insulating resin layer, wherein the another insulating resin layer has a function different from that of insulating resin layer.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-125302 | May 2010 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2011/062536 | May 2011 | US |
| Child | 13691139 | US |
