Semiconductor package structure and method for manufacturing the same

Abstract

A semiconductor package structure is disclosed. The structure includes a lead frame, a semiconductor chip, a plurality of metallic conducting wires, an encapsulation, a barrier layer and a pure tin layer, herein the lead frame has at least one die pad, a plurality of inner leads and outer leads. The semiconductor chip is disposed on the die pad. The metallic conducting wires electrically connect the semiconductor chip and the inner leads. The encapsulation packages of the semiconductor chip, the die pad, the metallic conducting wires and the inner leads. The barrier layer covers each of the outer leads to prevent an inter-metallic compound produced by the outer leads and pure tin. The pure tin layer covers the barrier layer to increase the solder wettability for the outer leads. Besides, a method for manufacturing the semiconductor package structure is disclosed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic flow diagram showing a conventional semiconductor package method to prevent the outer leads of the lead frame from producing whiskers;

FIG. 2 is a schematic flow diagram showing a semiconductor package method of the preferred embodiment of the present invention; and

FIGS. 3A-3D are a series of cross-sectional schematic diagrams of a semiconductor package structure of the preferred embodiment of the present invention.

Claims

1. A semiconductor package structure, comprising: a lead frame, wherein said lead frame includes a plurality of inner leads and outer leads;a semiconductor chip disposed on said lead frame, wherein said semiconductor chip is electrically connected to said inner leads;an encapsulation used to package said semiconductor-chip and said inner leads;a barrier layer covering each of said outer leads to prevent said outer leads and a pure tin from producing an inter-metallic compound, wherein said barrier layer is an environmentally friendly material without any heavy metal and has a good solder wettability with said outer leads and said pure tin; anda pure tin layer covering said barrier layer.

2. The semiconductor package structure of claim 1, wherein said barrier layer is made of pure nickel, pure titanium or chromium (VI).

3. The semiconductor package structure of claim 2, wherein said lead frame is made of pure copper or a copper alloy.

4. The semiconductor package structure of claim 2, further comprising: a plurality of metal conducting wires electrically connecting said semiconductor chip and said inner leads.

5. The semiconductor package structure of claim 2, wherein said lead frame further comprises a die pad to carry said semiconductor chip.

6. The semiconductor package structure of claim 1, wherein said lead frame is made of pure copper or a copper alloy.

7. The semiconductor package structure of claim 1, further comprising: a plurality of metal conducting wires electrically connecting said semiconductor chip and said inner leads.

8. The semiconductor package structure of claim 1, wherein said lead frame further comprises a die pad to carry said semiconductor chip.

9. A method for manufacturing a semiconductor package structure, said method comprising: providing a lead frame, wherein said lead frame includes a plurality of inner leads and outer leads;performing a semiconductor package step to dispose at least a semiconductor chip on said lead frame, wherein said semiconductor chip and said inner leads are packaged by an encapsulation after electrically connecting said semiconductor chip and said inner leads;forming a barrier layer on each of said outer leads to prevent said outer leads and pure tin from forming an inter-metallic compound, wherein said barrier layer is an environmentally friendly material without any heavy metal; andforming a pure tin layer on said barrier layer.

10. The method of claim 9, further comprising: cutting said lead frame to form a single package structure of one semiconductor chip.

11. The method of claim 10, wherein said barrier layer is made of pure nickel, pure titanium or chromium (VI).

12. The method of claim 10, wherein said lead frame is made of pure copper or a copper alloy.

13. The method of claim 10, wherein a method for forming said barrier layer is an electroplating method.

14. The method of claim 10, wherein a method for forming said pure tin layer is an electroplating method.

15. The method of claim 10, wherein said semiconductor chip is disposed on a die pad of said lead frame.

16. The method of claim 10, wherein said outer leads are bent to I-lead, J-lead, C-lead or a gull wing in the step of cutting said lead frame.

17. The method of claim 9, wherein said barrier layer is made of pure nickel, pure titanium or chromium (VI).

18. The method of claim 9, wherein said lead frame is made of pure copper or a copper alloy.

19. The method of claim 9, wherein a method for forming said barrier layer is an electroplating method.

20. The method of claim 9, wherein a method for forming said pure tin layer is an electroplating method.