Patent Application
20240421055
Example embodiments of the present disclosure relate generally to semiconductor packaging with embedded electromagnetic field (EMF) shielding protection using wire bonding.
Semiconductor packages for electronic devices continue to shrink in size and be placed closer together. These semiconductor packages as well as other components in the electronic devices generate electromagnetic fields. Thus the semiconductor packages are being increasingly exposed to greater amounts of electromagnetic fields. Semiconductor packages may also be required to download and/or process data at increasingly faster rates. The EMF exposure may cause the semiconductor packages to malfunction and/or generate errors, including in the data downloaded and/or processed.
New systems, apparatuses, and method for semiconductor packaging are needed. The inventor have identified numerous areas of improvement in the existing technologies and processes, which are the subjects of embodiments described herein. Through applied effort, ingenuity, and innovation, many of these deficiencies, challenges, and problems have been solved by developing solutions that are included in embodiments of the present disclosure, some examples of which are described in detail herein.
Various embodiments described herein relate to semiconductor packages, particularly semiconductor packages with embedded EMF shielding protection using wire bonding.
In accordance with some embodiments of the present disclosure, an example method is provided. The example method is of manufacturing a semiconductor package and may comprise: connecting a die to a base; creating a plurality of wire bonds each with a first end and a second end, wherein a first end of a first wire bond is connected to the die and a second end of the first wire bond is connected to the base, and wherein a first end of a second wire bond and a second end of the second wire bond are each connected to the base; applying molding to encapsulate the die and the plurality of wire bonds; removing a top side of the molding including breaking the plurality of wire bonds into a plurality of wires, wherein each of the plurality of wires is a shield wire connected to the base at a first end of the shield wire or a signal wire connected to the die at a first end of the signal wire; forming one or more redistribution layers on a first side of the molding, wherein the one or more redistribution layers include one or more signal pads and one or more ground planes, wherein each of the one or more signal pads is connected to at least one signal wires connected to the die, wherein at least one of one or more shield wires connects to the base is connected to the ground plane; applying one or more solder bumps to the one or more signal pads.
In some embodiments, the plurality of wire bonds surround the die.
In some embodiments, the plurality of wire bonds surround a portion of the dic.
In some embodiments, the semiconductor package is one of a plurality of semiconductor packages on a panel.
In some embodiments the method further comprises separating the semiconductor package from another semiconductor package of the plurality of semiconductor packages on the panel via singulation.
In some embodiments the method further comprises adjusting, prior to applying molding, an alignment of one or more of the plurality of wire bonds in a first direction.
In some embodiments the method further comprises creating, prior to forming one or more redistribution layers on a first side of the molding, one or more cavities in the molding, wherein the cavities are each associated with a signal wire connected to the die.
In some embodiments, creating one or more cavities is with laser ablation.
In some embodiments, forming one or more redistribution layers on a first side of the molding fills the one or more cavities with a conductive material.
In some embodiments, the one or more ground planes are separated from the one or more signal pads by one or more dielectric layers.
In accordance with some embodiments of the present disclosure, an example semiconductor package is provided. The example semiconductor package may comprise: a die with an active side; a base connected to a side of the die opposite the active side; a plurality of shield wires, wherein the plurality of shield wires are connected to the base and to one or more ground planes; a plurality of signal wires connected to the active side of the die and to one or more signal pads; wherein the plurality of shield wires and the plurality of signal wires are formed from portions of a plurality of wire bonds; a molding encapsulating the die, the shield wires, and the signal wires; a redistribution layer on top of the molding, wherein the redistribution layer include the one or more ground planes and the one or more signal pads; and a plurality of solder balls, wherein one or more of the plurality of solder balls are applied to the one or more signal pads.
In some embodiments, the plurality of shield wires surround the dic.
In some embodiments, the plurality of shield wires surround a portion of the die.
In some embodiments, the die is connected to the base with a gluc.
In some embodiments the semiconductor package further comprises an under bump metallization under each solder ball.
In some embodiments, the under bump metallization is comprised of nickel gold, titanium gold, or nickel palladium.
In some embodiments, a connection between at least one signal wire and the redistribution layer includes a cavity filled with a conductive material.
In some embodiments, the cavity was formed with laser ablation.
In some embodiments, at least one signal pad includes a plurality of copper layers including a first copper layer connected to a first signal wire and a second copper layer connected to the first copper layer, wherein the first copper layer has a first width, wherein the second copper layer has a second width that is larger than the first width and includes a portion of the second copper layer extending beyond the width of the first copper layer, and wherein second copper layer extending beyond the width of the first copper layer is connected to an under bump metallization associated with one of the plurality of solder balls.
In some embodiments, the one or more ground planes are separated from the one or more signal pads by one or more dielectric layers.
The above summary is provided merely for purposes of summarizing some example embodiments to provide a basic understanding of some aspects of the disclosure. Accordingly, it will be appreciated that the above-described embodiments are merely examples and should not be construed to narrow the scope or spirit of the disclosure in any way. It will also be appreciated that the scope of the disclosure encompasses many potential embodiments in addition to those here summarized, some of which will be further described below.
Having thus described certain example embodiments of the present disclosure in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:
Some embodiments of the present disclosure will now be described more fully herein with reference to the accompanying drawings, in which some, but not all, embodiments of the disclosure are shown. Indeed, various embodiments of the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.
As used herein, the term “comprising” means including but not limited to and should be interpreted in the manner it is typically used in the patent context. Use of broader terms such as comprises, includes, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and comprised substantially of.
The phrases “in various embodiments,” “in one embodiment,” “according to one embodiment,” “in some embodiments,” and the like generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).
The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.
If the specification states a component or feature “may,” “can,” “could,” “should,” “would,” “preferably,” “possibly,” “typically,” “optionally,” “for example,” “often,” or “might” (or other such language) be included or have a characteristic, that a specific component or feature is not required to be included or to have the characteristic. Such a component or feature may be optionally included in some embodiments or it may be excluded.
The use of the term “circuitry” as used herein with respect to components of a system or an apparatus should be understood to include particular hardware configured to perform the functions associated with the particular circuitry as described herein. The term “circuitry” should be understood broadly to include hardware and, in some embodiments, software for configuring the hardware. For example, in some embodiments, “circuitry” may include processing circuitry, communications circuitry, input/output circuitry, and the like. In some embodiments, other elements may provide or supplement the functionality of particular circuitry.
Various embodiments of the present disclosure are directed to improved systems, apparatuses, and methods for semiconductor packages with embedded EMF shielding protection using wire bonding.
Semiconductor packages continue to shrink in size and be utilized in environments with increasing amounts of electromagnetic fields, such as in mobile phones, portable electronics, and the like. The increase in EMF exposure may cause a semiconductor package to generate errors while processing and/or transmitting data. EMF exposure may be minimized or mitigated with the semiconductor packaging with EMF shielding protection using wire bonding described herein. This may increase the performance of such semiconductor devices as well as increase the life of these semiconductor packages.
In accordance with the present disclosure, semiconductor packages have exterior wire bonds that may be broken to create two wires. Portions of the broken wire bonds may be shield wires and/or signal wires. The shield wires may be placed around an exterior portion of the semiconductor package. These shield wires may be connected a ground plane on a first side of the semiconductor package to a base on the second side of the semiconductor package. The shield wires may create a cage around all of or a portion of a die of the semiconductor package. This cage may ground signals generated by EMF the semiconductor package is exposed to. The signal wires may be connected to one or more of a plurality of signals pads to transfer signals between the die and an external device via a plurality of solder balls. Examples of the semiconductor package may be flip chips that have solder balls that connect one or more signal pads of the semiconductor device to one or more other circuitries of an electronic device.
Methods described herein are directed to manufacturing and using a semiconductor packaging with EMF shielding using wire bonds. Methods are also described herein that are directed to manufacturing a plurality of semiconductor packages using wire bonds for EMF shielding. For example, a panel of dies may be used to create a plurality of semiconductor packages that may later be separated by singulation.
Embodiments of the present disclosure include systems and apparatuses for semiconductor packages with embedded EMF shielding protection using wire bonding as described herein and may be implemented in various embodiments.
It will be readily appreciated that while only one of the signal pads 130 and signal pad solder balls 132 are referenced with numbers, the semiconductor package 100 may include a plurality of each. Each of the signal pads 130 may be separated from the ground plane 120 by one or more layers and/or portions of dielectric material (e.g., dielectric layer 110). The semiconductor package 100 may be a flip chip, and when it is used in an electronic device the plurality of solder balls may connect the semiconductor package to other circuitries of the electronic device. In various embodiments, the semiconductor package 100 may be a generally square shape. It will be readily appreciated that the semiconductor package 100 may take other shapes and/or dimensions, particularly as required by an electronic device.
The semiconductor package 100 includes a plurality of wires 182. As described herein, these wires 182A-D are created from wire bonds that were encapsulated in molding 150, which holds the wires 182A-D in place. Wires 182A and 182C connect the base 170 to the ground plane 120. The wires 182B and 182D connect the die 160 to a respective signal pad 130A, 130B. The wires 182B, 182D are offset from where the signal pad solder balls 132A, 132B respectively connect to the signal pads 130. In various embodiments, the wires 182B, 182D are not offset and may be aligned with where the signal pad solder balls 132A, 132B respectively connect to the signal pads 130A, 130B. Each of the signal pads 130 is formed in a redistribution layer (RDL) on top of the molding 150. The RDL includes the dielectric layer 110, the ground plane 120, and the signal pads 130. The signal pads are each connected to a solder ball 132. For example, signal pad 130A is connected to signal pad solder ball 132A and signal pad 130B is connected to signal pad solder ball 132B.
As illustrated in
In various embodiments, and as described further herein, these shield wires 182 on the exterior may formed from wire bonds either connecting the base 170 to the die 160 or connecting to base 170 at both ends of the wire bonds. The ground plane solder ball 122 and signal pad solder balls 132A, 132B are illustrated on top of the dielectric layer 110 as they do not connect to one or more UBM layers at the cross-section of B-B.
As illustrated in
In various embodiments, the wires around the exterior of the semiconductor package 100 may surround a portion of the die 160 or all of the die 160.
As illustrated in
Misalignments of the die 160 may cause a wire connecting the die 160 to the RDL 190 to be out of position as the small sizes require precision. The misalignments may cause a connection to fail or to be more likely to fail under stress. As described herein, the semiconductor packages 100 with EMF shielding using wire bonds may address and/or correct for such misalignments. This increases the yield of a panel or the like applying the present disclosure. For example, panel 400, after completion of a plurality of operations described herein, may have individual semiconductor packages 100 separated from the panel 400 with one or more singulation operations.
It should be readily appreciated that the embodiments of the systems and apparatuses, described herein may be configured in various additional and alternative manners in addition to those expressly described herein.
At operation 502, a die 160 is connected to a base 170. For example, a die 160 may be connected to a bondable surface of the base 170 using a glue 162 or the like. In various embodiments, a plurality of die 160 may be connected to a base 170 of a panel 400. This operation is further described in relation to
At operation 504, wire bonds are created. A plurality of wire bonds 180 are created, including one or more wire bonds 180 connecting the die 160 and the base 170 and one or more wire bonds 180 connecting both sides of the wire bond 180 to the base 170. The wire bonds 180 may be created around all of or a portion of the exterior of the die 160. This operation is further described in relation to
At operation 506, wire bonds may be adjusted. In various embodiments, a wire bond may be adjusted. While the adjustment of the wire bond is described as a separate operation herein, it will be appreciated that the adjustment may be performed during or contemporaneously with the creation of a wire bond. A determination may be made that one or more wire bonds 180 need to be adjusted. In various embodiments, the RDL 190 may be formed without allowing for adjustment of the location of one or more portions of the RDL 190. For example, a panel 400 with a plurality of die 160 may have an RDL 190 formed for all of the die 160 at one time. If any of the die 160 are determined to be out of alignment, these dies 160 may need to be aligned or the wire bonds 180 may be adjusted to allow for the misalignment. This operation is further described in relation to
At operation 508, molding 150 is applied. The molding 150 encapsulates the die and wire bonds 180, including being above the die 160 and wire bonds 180. The molding 150 will hold the die 160 and wire bonds 180 in place. This operation is further described in relation to
At operation 510, a top side of the molding 150 is removed to exposes wire 182. Removing the top side of the molding 150 may be done by grinding the molding 150 down so that the wire bonds 180 are broken, each of which creates two separate wires 182 from different portions of a wire bond 180. Each of these separate wires 180 may have an open end now exposed due to where the molding 150 was removed and a connected end that is connected to a die 160 for a signal wire 182 or the base 170 for a shield wire 182. This operation is further described in relation to
At operation 512, one or more cavities 198 may be created for the wires 182. For example, and for each of the signal wires 182 connected to the die 160, the end of the signal wire 182 not connected to the die 160 may have the molding 160 around the end portion of the wire 182 removed to create a cavity 198 in the molding 160. In various embodiments, a cavity 198 may be created by a laser, such as with laser ablation. This operation is further described in relation to
At operation 514, one or more RDL 190 may be formed. The formation of the RDL 190 may generate the dielectric layer 110, the ground plane 120, the signal pads 130, and the UBM 140. This operation is further described in relation to
At operation 516, solder bumps (e.g., 122, 132) may be applied. The solder bumps may be applied to one or more portions of the RDL 190 with UBM 140. This operation is further described in relation to
The RDL 190 is separated from the die 160 with wires (e.g., 182B, 182C) connecting the die 160 to associated signal pads 130A, 130B. The separation between the RDL 190 and the die 160 by these signal wires 182B, 182D allows for improved operation of the semiconductor package due to the RDL 190 and the die 160 having different coefficient of thermal expansion. Under thermal expansion the RDL 190 and die 160 may expand or contract and cause stress on the other, which may lead to delamination and the die and/or breaking or the deterioration of a connection. The signal wires 182 of the present disclosure allows for a lowering of stresses and an increase in reliability between the RDL 190 and the die 160.
An alignment operation may adjust a wire 182 for connection to the RDL layer 190. In various embodiments where multiple die 160 are prepared together in a panel 400, one or more adjustments may improve the yield of the panel 400 as the plurality of die 160 are having, for example, the RDL formed for all of the die 160 at the same time.
In various embodiments of manufacturing panels, a determination may be made if one or more die 160 are misaligned. If any die is misaligned, one or more adjustments to be made may be determined. During the manufacturing of the semiconductor packages 100, the one or more adjustments may be made.
In various embodiments, the filling of the cavity 198 with copper may provide for an improved connection to a wire. It may also provide improved mechanical grip and adhesion of the connection between the die 160 and the signal pad 130 (or between the base 170 and the ground plane 120 for a wire not illustrated).
Operations and/or functions of the present disclosure have been described herein, such as in flowcharts or figures associated with flowcharts. While operations and/or functions are illustrated in a particular order, this should not be understood as requiring that such operations and/or functions be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, operations and/or functions in alternative ordering may be advantageous. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results. Thus, while particular embodiments of the subject matter have been described, other embodiments are within the scope of the following claims.
While this specification contains many specific embodiments and implementation details, these should not be construed as limitations on the scope of any disclosures or of what may be claimed, but rather as descriptions of features specific to particular embodiments of particular disclosures. Certain features that are described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
While this detailed description has set forth some embodiments of the present invention, the appended claims cover other embodiments of the present invention which differ from the described embodiments according to various modifications and improvements.
Within the appended claims, unless the specific term “means for” or “step for” is used within a given claim, it is not intended that the claim be interpreted under 35 U.S.C. § 112, paragraph 6.
This application claims priority to U.S. Provisional Patent Application No. 63/521,247 filed on Jun. 15, 2023, which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63521247 | Jun 2023 | US |
