Patent Application
20080315436
1. Field of the Invention
The present invention relates to semiconductor wafers, and more particularly, to wafer fabrication and packaging of integrated circuits of wafers.
2. Background Art
Integrated circuit (IC) chips or dies from semiconductor wafers are typically interfaced with other circuits using a package that can be attached to a printed circuit board (PCB). One such type of IC die package is a ball grid array (BGA) package. BGA packages provide for smaller footprints than many other package solutions available today. A BGA package has an array of solder ball pads located on a bottom external surface of a package substrate. Solder balls are attached to the solder ball pads. The solder balls are reflowed to attach the package to the PCB.
BGA packages are available in a variety of types. An example type of BGA package is a fine pitch BGA (FPBGA or FBGA) package. In a FBGA package, a chip is mounted to a substrate by a die attach material. Wirebonds electrically connect signals of the die to conductive features on the substrate. A mold compound encapsulates the die, wirebonds, and the entire top surface of the substrate. Solder balls of a FBGA package are smaller than solder balls of other BGA package types, such as plastic BGA (PBGA) packages, and a smaller ball pitch is used to space the solder balls.
Another type of BGA package is a wafer-level BGA (WLBGA) package. Wafer-level BGA packages have several names in industry, including wafer level chip scale packages (WLCSP), among others. In a wafer-level BGA package, the solder balls are mounted directly to the IC chip when the IC chip has not yet been singulated from its fabrication wafer. Wafer-level BGA packages can therefore be made very small, with high pin out, relative to other IC package types including traditional BGA packages.
Millions of integrated circuit packages are needed each year to interface integrated circuit chips with devices. Thus, what are needed are improved chip fabrication and packaging techniques that can help meet the high quantity production needs for integrated circuit packages.
Methods, systems, and apparatuses for semiconductor wafers and for integrated circuit chip packaging techniques are provided. In an aspect of the present invention, a wafer is fabricated that supports multiple different packaging techniques. The wafer may be fabricated prior to deciding on a particular packaging technique for chips of the wafer. Chips of the wafer can be assembled into different types of integrated circuit packages without modifying the chip layout.
In an example, a wafer is formed to have a plurality of integrated circuit regions. A first plurality of terminals is formed on a surface of the wafer in a central region of each integrated circuit region. A second plurality of terminals is formed on the surface of the wafer in a peripheral region of each integrated circuit region. For each integrated circuit region, each terminal of the second plurality of terminals is electrically coupled through the wafer to at least one terminal of the first plurality of terminals. The integrated circuit regions can be separated into chips that can be packaged in multiple ways. In an aspect, a wafer may be fabricated that supports wire-bond packaging and flip chip packaging for chips/dies of the wafer.
These and other objects, advantages and features will become readily apparent in view of the following detailed description of the invention. Note that the Summary and Abstract sections may set forth one or more, but not all exemplary embodiments of the present invention as contemplated by the inventor(s).
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.
The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.
The present specification discloses one or more embodiments that incorporate the features of the invention. The disclosed embodiment(s) merely exemplify the invention. The scope of the invention is not limited to the disclosed embodiment(s). The invention is defined by the claims appended hereto.
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Furthermore, it should be understood that spatial descriptions (e.g., “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” etc.) used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner.
The example embodiments described herein are provided for illustrative purposes, and are not limiting. The examples described herein may be adapted to various types of integrated circuit packages. Furthermore, additional structural and operational embodiments, including modifications/alterations, will become apparent to persons skilled in the relevant art(s) from the teachings herein.
According to embodiments of the present invention provide, a semiconductor wafer is fabricated that supports multiple different packaging techniques. For example, in an embodiment, a wafer is fabricated that supports wire-bond packaging, such as used for standard fine-pitch ball grid array (FBGA) packages, or wafer level ball grid array (WLBGA) packaging for chips/dies of the wafer.
Embodiments allow for flexibility in chip packaging processes. Conventionally, a wafer is fabricated after an order for packages is received because the chips must be physically formed specific to the particular package type. For example, chips targeted for wire bond packaging must have pads/terminals located at perimeter edges of an active surface of the chips. Chips targeted for flip chip packaging may have pads/terminals located in an array throughout their active surface. It is typically not economically feasible to pre-form a large number of wafers with chips dedicated to a particular packaging type, because many such pre-formed wafers may go unused if orders for them are not placed. Because of this, conventional packaging processes typically receive wafers fabricated after an order for packages is received. A time required to fabricate a wafer can be very long, including months or longer. Thus, the time to conventionally fill a package order can be long due to the wafer fabrication and chip packaging both occurring after the package order is received.
In contrast, in embodiments of the present invention, wafers are fabricated to include chips that are packaging process flexible, and thus the wafers can be pre-fabricated. When a chip package order is received, the pre-fabricated wafers can immediately be used by a packaging process to assemble the packages. Thus, the packages can be assembled and delivered sooner than in conventional packaging processes, avoiding the additional months conventionally needed to fabricate wafers after receiving an order.
In embodiments, wafers that can be used in different packaging schemes can be tracked with a single part number because they are identical, as compared to conventional wafers for different packaging schemes needing different part numbers because they are configured differently. Embodiments save manufacturing costs in requiring a single mask set for a wafer that can be used in different packaging processes, rather than multiple mask sets being needed for multiple conventional wafers for different packaging schemes.
For example,
As shown in
Electrical connections 112 are further coupled to electrical signals internal to chip 100. For example, electrical connection 112a may be coupled to an electrical signal of chip 100 that is desired to be accessible outside of chip 100, such as an I/O signal, a test signal, a power signal, a ground signal, etc. In this manner, the electrical signal coupled internal to chip 100 to electrical connection 112a is electrically coupled to both of terminals 108a and 110a. Thus, either of terminals 108a and 110a of chip 100 may be used to externally access the electrical signal. All signals of interest of chip 100 may be electrically coupled to pairs of terminals 108 and 110 by respective electrical connections 112, to be externally accessible to chip 100 in a redundant manner.
Terminals 108 and 110 and electrical connections 112 may be formed by standard wafer fabrication processes, such as by photolithographic techniques, etching techniques, thin film deposition techniques (e.g., sputtering, chemical vapor deposition (CVD), evaporative deposition, epitaxy, etc.), and/or other techniques. Electrical connections 112 may include one or more electrically conductive routes (e.g., metal traces, semiconductor material routes), electrically conductive vias, RDL (redistribution layer) layers, etc., formed on a single layer or multiple layers of the wafer from which chip 100 is derived. Electrical connections 112 are shown in
Flowchart 500 begins with step 502. In step 502, a plurality of electrical connections is formed in the wafer in a first integrated circuit region. For example,
In step 504, a first plurality of terminals is formed on a surface of the semiconductor wafer in a central region of the first integrated circuit region. For example, as shown in
In step 506, a second plurality of terminals is formed on the surface of the semiconductor wafer in a peripheral region of the first integrated circuit region, wherein each terminal of the second plurality of terminals is electrically coupled by an electrical connection through the wafer to at least one terminal of the first plurality of terminals. For example, as shown in
Furthermore, as shown in
Note that in an embodiment, the forming of terminals according to steps 504 and 506 may be performed simultaneously. Note that flowchart 500 can be performed for all of the integrated circuit regions of wafer 400.
Subsequent to fabrication of wafer 400 as described above, flowchart 700 shown in
In step 702, a semiconductor wafer is received having a plurality of integrated circuit regions on a surface of the semiconductor wafer, each integrated circuit region of the plurality of integrated circuit regions having a first plurality of terminals in a central region of the integrated circuit region and a second plurality of terminals in a peripheral region of the integrated circuit region, wherein each terminal of the second plurality of terminals is electrically coupled through the wafer to at least one terminal of the first plurality of terminals. For example, wafer 400 may be received, having a plurality of integrated circuit regions formed as described above for integrated circuit region 602.
In step 704, each integrated circuit region is packaged. For example, each integrated circuit region 602 of wafer 400 may be packaged, according to one of the multiple package types for which the wafer is adapted. In an embodiment, performing step 704 includes electrically isolating terminals of one of the first plurality of terminals 108 or the second plurality of terminals 110 for each integrated circuit region, although this is not required. Examples of step 704 are described in detail as follows.
For example, in an embodiment, integrated circuit region 602 is configured to be packaged according to either of a wire bond packaging process or a wafer-level BGA packaging process. If a wafer-level BGA packaging process is selected (e.g., according to a customer request, etc.), flowchart 800 shown in
Flowchart 800 begins with step 802. In step 802, a passivation layer is formed over the surface of the semiconductor wafer. For example, a passivation layer may be formed on surface 402 of wafer 400 shown in
In step 804, an opening is formed through the passivation layer at each terminal of the first plurality of terminals. For example, as shown in
In step 806, a conductive ball or bump is attached to each terminal of the first plurality of terminals through the opening at each terminal. As shown in
In step 808, the semiconductor wafer is singulated to separate the plurality of integrated circuit regions into a plurality of separate integrated circuit chip packages. For example, wafer 400 is singulated (e.g., diced, sawed, etc.) to separate integrated circuit regions 602 (e.g., shown in
In step 810, a first integrated circuit chip package of the plurality of separate integrated circuit chips packages is flip chip mounted to a substrate. Step 810 is optional. For example, step 810 may be performed to flip chip attach a wafer-level BGA package formed by step 808 to a subsequent substrate to form a larger package, such as a chip-scale package. For example, package 900 shown in
If a wire bonding type packaging process is selected prior to step 704 of flowchart 700 shown in
Flowchart 1000 begins with step 1002. In step 1002, the semiconductor wafer is singulated to separate the plurality of integrated circuit regions into a plurality of separate integrated circuit chips. For example, wafer 400 is singulated (e.g., diced, sawed, etc.) to separate integrated circuit regions 602 (e.g., shown in
Steps 1004-1008 described below may be performed on as many of chips 100 formed from wafer 400 in step 1002, as desired.
In step 1004, a first integrated circuit chip of the plurality of separate integrated circuit chips corresponding to the first integrated circuit region is mounted to a surface of an integrated circuit package substrate. For example, chip 100 of
In step 1006, a plurality of bond wires is coupled between the second plurality of terminals and conductive features on the surface of the integrated circuit package substrate. For example, as shown in
In step 1008, the first integrated circuit chip and the plurality of bond wires are encapsulated on the surface of the integrated circuit package substrate. For example, as shown in
Note that FBGA package 1100 may be further processed, as desired. For example, as shown in
Other configurations for FBGA package 1100 are also within the scope of embodiments of the present invention. For example package 1100 in
Flowcharts 800 and 1000 respectively result in a wafer level BGA package (e.g., wafer level BGA package 900) and a wire bonded package (e.g., FBGA package 1100) from a common chip configuration that can be sold to customers, mounted in devices, or otherwise used as desired.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
