This disclosure relates to the field of integrated circuits. More particularly, this disclosure relates to metal silicide in integrated circuits.
An integrated circuit may include logic circuits and analog circuits. The logic circuits may have complementary metal oxide semiconductor (CMOS) gates, that is, gates of n-channel metal oxide semiconductor (NMOS) transistors and p-channel metal oxide semiconductor (PMOS) transistors. To reduce the size and fabrication cost of the integrated circuit, it is desirable to shrink the NMOS transistors and PMOS transistors in the logic circuits. Metal silicide, formed by a self-aligned process, is commonly formed on sources and drains of the NMOS transistors and PMOS transistors to reduce electrical resistances of the transistors and thus improve the operating speed of the logic circuits. One or more of the analog circuits may include components having a silicide block layer, which is a patterned dielectric layer over silicon that blocks formation of the metal silicide. Silicon dioxide is a preferred material for silicide block layers in analog circuits, as other materials such as silicon nitride and silicon oxy-nitride tend to trap charge, degrading performance of the analog circuits. The silicide block layer must be sufficiently robust to withstand deglaze etches and other wet etch processes. Robustness in the silicide block layer is commonly achieved by elevated deposition temperatures, 600° C. or higher, or correspondingly high temperatures in a densification process after deposition, for example, a furnace process at 650° C. for an hour. Such temperature regimens tend to cause diffusion of dopants in the NMOS and PMOS logic circuits, degrading performance factors such as off-state current. As smaller transistors are used in the logic circuits, this problem is exacerbated.
The present disclosure introduces a method of forming an integrated circuit having silicide block integrated with CMOS transistors. The sources, drains, and halo regions of the NMOS transistors and PMOS transistors are implanted with appropriate dopants. Prior to annealing the PMOS sources and drains, a silicide block layer, which includes primarily silicon dioxide and is free of silicon nitride and silicon oxy-nitride, is formed at less than 400° C. A subsequent spike anneal process concurrently anneals the PMOS sources and drains and densifies the silicide block layer. The spike anneal heats the PMOS sources and drains and the silicide block layer to greater than 1000° C. for at least 1 second and less than 10 seconds. The NMOS transistors have drain junctions with depths less than 120 nanometers. The NMOS transistors also have p-type halo regions containing boron adjacent to the drains. The NMOS transistors and PMOS transistors are laterally separated by a shallow trench isolation (STI) oxide layer. After patterning the silicide block layer, a wet deglaze process prepares the surfaces of the sources and drains for metal silicide formation. The wet deglaze removes less than 25 percent of the silicide block layer, and exposes the sides of the drains on the NMOS transistors less than 20 percent of the depth of the drain junction. The metal silicide on the drains of the NMOS transistors does not extend down sides of the drains, directly adjacent to the STI oxide layer, more than 20 percent of the depth of the drain junction.
The present disclosure is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure.
An integrated circuit which includes an NMOS transistor, a PMOS transistor, and a component with a silicide block layer, may be formed by implanting the sources, drains, and halo regions of the NMOS transistor and the PMOS transistor with appropriate dopants. In particular, the halo regions of the NMOS transistor are implanted with boron. Prior to annealing the PMOS source and drain, a silicide block layer, which includes primarily silicon dioxide and is free of silicon nitride and silicon oxy-nitride, is formed at less than 400° C. A subsequent spike anneal process concurrently anneals the PMOS source and drain and densifies the silicide block layer. Densification of the silicide block layer reduces a hydrogen content in the silicide block layer and increases covalent bonding between silicon and oxygen in the silicide block layer. Densification of the silicide block layer is manifested as a reduction in etch rate of the silicide block layer in an aqueous solution of hydrofluoric acid. The spike anneal heats the PMOS source and drain and the silicide block layer to greater than 1000° C. for at least 1 second and less than 10 seconds. After patterning the silicide block layer, a wet deglaze process removes native oxide on surfaces of the sources and drains for metal silicide formation. The wet deglaze removes less than 25 percent of the silicide block layer, and exposes the side of the drain on the NMOS transistor to a depth that is less than 20 percent of the depth of the drain junction. A layer of metal is formed on the sources and drains and over the silicide block layer. The layer of metal is heated to react the metal with exposed silicon to form metal silicide. The metal silicide is not formed on silicon under the silicide block layer. Unreacted metal of the metal layer is subsequently removed.
The integrated circuit may also include a localized oxidation of silicon (LOCOS) oxide layer. The LOCOS oxide layer may be present in components of analog circuits, providing an oxide layer thinner than the STI oxide layer. Formation of the LOCOS oxide layer includes a wet etch process to remove a silicon dioxide layer; the wet etch process combined with the wet deglaze does not expose the side of the drain on the NMOS transistor more than 20 percent of the depth of the drain junction.
For the purposes of this disclosure, the term “instant top surface” of an integrated circuit is understood to refer to a top surface of the integrated circuit which exists at the particular step being disclosed. The instant top surface may change from step to step in the formation of the integrated circuit. For the purposes of this disclosure, the terms “lateral” and “laterally” are understood to refer to a direction parallel to a plane of the instant top surface of the integrated circuit.
It is noted that terms such as top, bottom, over, above, and under may be used in this disclosure. These terms should not be construed as limiting the position or orientation of a structure or element, but should be used to provide spatial relationship between structures or elements.
For the purposes of this disclosure, it will be understood that, if an element is referred to as being “adjacent” to another element, it may be directly adjacent to the other element, or intervening elements may be present. If an element is referred to as being “directly adjacent” to another element, it is understood there are no other intentionally disposed intervening elements present.
An STI oxide layer 114 is formed in isolation trenches in the substrate 102. An example process for forming the STI oxide layer 114 may include forming a chemical mechanical polish (CMP) stop layer of silicon nitride over the substrate 102, and etching the isolation trenches through the CMP stop layer and into the substrate 102. A thermal oxide liner 116 is formed on sidewalls and bottoms of the isolation trenches by a thermal oxidation process. Fill oxide 118 is formed on the thermal oxide liner 116 and over the CMP stop layer using a plasma enhanced chemical vapor deposition (PECVD) process using tetraethyl orthosilicate (TEOS), a high density plasma (HDP) process, a high aspect ratio process (HARP) using TEOS and ozone, an atmospheric chemical vapor deposition (APCVD) process using silane, or a sub-atmospheric chemical vapor deposition (SACVD) process using dichlorosilane. The fill oxide 118 is removed from over the CMP stop layer by an oxide CMP process, and the CMP stop layer is subsequently removed. A subsequent deglaze wet etch removes a portion of the thermal oxide liner 116 at edges of the substrate 102 directly adjacent to the STI oxide layer 114, as depicted in
A top surface 120 of the STI oxide layer 114 may be less than 10 nanometers higher than a top surface 122 of the semiconductor material 104 in the area for the NMOS transistor 106 and in the area for the PMOS transistor 108. Forming the STI oxide layer 114 so that the top surface 120 is less than 10 nanometers higher than the semiconductor material 104 may advantageously provide process latitude for forming gates of the NMOS transistor 106 and the PMOS transistor 108, as larger differences between the top surfaces 120 and 122 has been known to adversely affect a photolithographic process to form a gate mask and a reactive ion etch (RIE) process to form the gates.
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A NMOS gate 130 is formed on the NMOS gate dielectric layer 126 in the area for the NMOS transistor 106. A PMOS gate 132 is formed on the PMOS gate dielectric layer 128 in the area for the PMOS transistor 108. The NMOS gate 130 and the PMOS gate 132 may have different structures and compositions, to independently improve performances of the NMOS transistor 106 and the PMOS transistor 108. A gate layer resistor 134 is formed on the LOCOS oxide layer 124 in the area for the second component 112. The NMOS gate 130, the PMOS gate 132, and the gate layer resistor 134 may include polycrystalline silicon, and at least a portion of the NMOS gate 130, the PMOS gate 132, and the gate layer resistor 134 may be formed concurrently. The NMOS gate 130 and the PMOS gate 132 may be formed, for example, by forming a layer of gate material such as polycrystalline silicon over the substrate 102, the STI oxide layer 114, and the LOCOS oxide layer 124. A thickness of the layer of gate material in the areas for the NMOS transistor 106 and the PMOS transistor 108 may be affected by the height of the top surface 120 of the STI oxide layer 114 adjacent to the areas for the NMOS transistor 106 and the PMOS transistor 108 relative to the top surface 122 of the substrate 102, in that variations in the height of the top surface 120 of the STI oxide layer 114 may produce corresponding variations in the thickness of the layer of gate material. A layer of photoresist may be formed over the layer of gate material, along with anti-reflection layers and hard mask layers. The thicknesses of the photoresist, anti-reflection layers, and hard mask layers are similarly adversely affected by variations in the height of the top surface 120 of the STI oxide layer 114 relative to the top surface 122 of the substrate 102. The photoresist is patterned by a photolithographic process to form a gate mask. A physical linewidth of the gate mask in the areas for the NMOS gate 130 and the PMOS gate 132 may be affected by the thicknesses of the photoresist, anti-reflection layers, and hard mask layers. Thicker photoresist may produce larger physical linewidths of the gate mask, and vice versa. Subsequently, an RIE process is used to etch the layer of gate material where exposed by the gate mask to form the NMOS gate 130, the PMOS gate 132, and the gate layer resistor 134. Physical linewidths of the NMOS gate 130 and the PMOS gate 132 may be affected by the physical linewidth of the gate mask, as well as by the thickness of the layer of gate material. Thicker material may produce larger linewidths of the gates 130 and 132, and vice versa. Thus, maintaining the top surface 120 of the STI oxide layer 114 within 10 nanometers of the top surface 122 of the substrate 102 may advantageously produce consistent physical linewidths of the gates 130 and 132, sometimes referred to as physical gate lengths.
A silicon dioxide layer 136 is formed on the gates 130 and 132 and the gate layer resistor 134, and may extend onto the top surface 122 of the semiconductor material 104 where exposed, for example in the area for the first component 110. The silicon dioxide layer 136 may be formed by a thermal oxidation process, or by a conformal PECVD process.
N-type source and drain extensions 138 are formed in the semiconductor material 104 in the area for the NMOS transistor 106. The n-type source and drain extensions 138 extend partway under the NMOS gate 130, as depicted in
P-type source and drain extensions 142 and n-type halo regions 144 are formed in the semiconductor material 104 in the area for the PMOS transistor 108, by a similar process sequence. Boron may be implanted to form the p-type source and drain extensions 142, and phosphorus may be implanted to form the n-type halo regions 144.
The silicon dioxide layer 136 may optionally be augmented by additional layers of dielectric material between forming the n-type source and drain extensions 138 and the p-type source and drain extensions 142. Additional elements, such as carbon, may be implanted during formation of the n-type source and drain extensions 138 and the p-type source and drain extensions 142 to control diffusion of the implanted dopants.
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N-type dopants such as phosphorus and arsenic are implanted into the semiconductor material 104 in the area for the NMOS transistor 106 to form NMOS source and drain implanted regions 148, extending partway under the gate sidewall spacers 146, and partly overlapping the n-type source and drain extensions 138. The n-type dopants may be implanted with a dose greater than 1×1015 cm−2 to attain low resistance in the source and drain of the NMOS transistor 106.
P-type dopants such as boron are implanted into the semiconductor material 104 in the area for the PMOS transistor 108 to form PMOS source and drain implanted regions 150, extending partway under the gate sidewall spacers 146, and partly overlapping the p-type source and drain extensions 142. The p-type dopants may be implanted with a dose greater than 3×1015 cm−2 to attain low resistance in the source and drain of the PMOS transistor 108.
N-type dopants are also implanted into the semiconductor material 104 in the area for the first component 110 to form a resistor implanted region 152. The resistor implanted region 152 may optionally be formed concurrently with the NMOS source and drain implanted regions 148.
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The spike anneal process 156 may be performed in a rapid thermal processor (RTP) tool. The spike anneal process 156 heats the NMOS source and drain implanted regions 148, the PMOS source and drain implanted regions 150, and the silicide block layer 154 to a temperature greater than 1000° C. for more than 1 second, but less than 10 seconds. Moreover, the spike anneal process 156 heats the NMOS source and drain implanted regions 148, the PMOS source and drain implanted regions 150, and the silicide block layer 154 to a temperature greater than 900° C. for no more than 30 seconds. The spike anneal process 156 may be extended to a flash anneal process, which heats the NMOS source and drain implanted regions 148, the PMOS source and drain implanted regions 150, and the silicide block layer 154 to a temperature greater than 1200° C. for a time period of microseconds to milliseconds. The spike anneal process 156 may be distinguished from a rapid thermal anneal process which heats to a temperature of 800° C. to 1000° C. for a time period greater than 10 seconds. The spike anneal process 156 may also be distinguished from a furnace process which heats for a time period of minutes to hours. The spike anneal process 156 may advantageously anneal the NMOS source and drain implanted regions 148 and the PMOS source and drain implanted regions 150 with less diffusion of the boron dopants in the p-type halo regions 140 compared to an anneal process having a longer time scale, such as a rapid thermal anneal process or a furnace anneal process. Concurrently annealing the NMOS source and drain implanted regions 148 and the PMOS source and drain implanted regions 150, and densifying the silicide block layer 154 may advantageously reduce diffusion of the boron dopants in the p-type halo regions 140 compared to using separate anneal and densification processes. The spike anneal process 156 may advantageously reduce boron diffusion from the PMOS source and drain implanted regions 150 into the silicon dioxide layer 136 in the area for the PMOS transistor 108, compared to an anneal with a longer time frame or to using separate anneal and densification processes. Boron in the silicon dioxide layer 136 affects an etch rate during a subsequent etch process to pattern the silicide block layer 154, causing overetch in the area for the NMOS transistor 106.
Referring to
The silicide block layer 154 and the silicon dioxide layer 136 are removed where exposed by the silicide block mask 164. The silicide block layer 154 and the silicon dioxide layer 136 may be removed by an RIE process, stopping on the semiconductor material 104 and the gate layer resistor 134. Using the spike anneal process 156 of
The silicide block mask 164 is subsequently removed, for example, with an oxygen plasma process, which forms a native oxide on the top surface 122 of the semiconductor material 104. Removal of the silicide block mask 164 forms a thicker native oxide on more damaged silicon, requiring a longer deglaze to prepare the silicon for subsequent formation of metal silicide. Thus, using the spike anneal process 156 may reduce the thickness of the native oxide.
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The metal silicide 170 forms on exposed surfaces of the NMOS source and drain regions 158. By using the spike anneal process 156 of
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Contacts 174 are formed through the PMD layer 172 to make electrical connections to the metal silicide 170. The contacts 174 may be formed by etching contact holes through the PMD layer 172, and forming a titanium liner, by sputtering or an ionized metal plasma (IMP) process, on the PMD layer 172 and extending into the contact holes. A titanium nitride liner is formed, by reactive sputtering or atomic layer deposition (ALD), on the titanium liner. A layer of tungsten is formed, by a metal organic chemical vapor deposition (MOCVD) process, on the titanium nitride liner, filling the contact holes. The tungsten, titanium nitride and titanium are removed from over a top surface of the PMD layer 172 by a tungsten CMP process, leaving the tungsten fill metal, titanium nitride liner and titanium liner in the contact holes to provide the contacts 174.
While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.