Claims
- 1. A method for forming solder bumps on a microelectronic device having a substrate and a contact pad on said substrate, wherein said contact pad has an exposed surface portion, said method comprising the steps of:
- forming a titanium barrier layer on said contact pad, wherein said barrier layer covers said exposed surface portion of said contact pad and extends over said substrate;
- forming an under bump metallurgy layer on said barrier layer opposite said substrate, said under bump metallurgy layer comprising a chromium layer on said barrier layer, a phased layer of chromium and copper on said chromium layer opposite said barrier layer, and a copper layer on said phased layer opposite said chromium layer;
- forming a solder bump on said under bump metallurgy layer opposite said exposed surface portion of said contact pad and opposite said titanium barrier layer thereby defining exposed and unexposed portions of said under bump metallurgy layer;
- applying a chemical etchant to said exposed portions of said under bump metallurgy layer wherein said chemical etchant attacks said under bump metallurgy layer preferentially with respect to said solder bump and said titanium barrier layer thereby defining an exposed portion of said titanium barrier layer; and
- applying a titanium etchant to said exposed portion of said titanium barrier layer wherein said titanium etchant selectively attacks said titanium barrier layer preferentially with respect to said solder bump, said copper layer, said phased layer, and said chromium layer.
- 2. A method according to claim 1 wherein said contact pad comprises a titanium contact pad.
- 3. A method according to claim 1 wherein said titanium etchant comprises hydrofluoric acid buffered with ammonium fluoride.
- 4. A method according to claim 1 wherein said step of applying a chemical etchant further comprises the steps of:
- applying a copper etchant to said exposed portion of said copper layer wherein said copper etchant selectively attacks said copper layer and said copper portion of said phased layer preferentially with respect to said solder bump, said chromium layer, and said titanium barrier layer; and
- applying a chromium etchant to said chromium portion of said phased layer and said chromium layer wherein said chromium etchant selectively attacks said chromium portion of said phased layer and said chromium layer preferentially with respect to said solder bump, said copper layer, and said titanium barrier layer.
- 5. A method according to claim 4 wherein said copper etchant comprises a mixture of ammonium hydroxide and hydrogen peroxide, and wherein said chromium etchant comprises a mixture of hydrochloric acid and water.
- 6. A method according to claim 1 wherein said step of forming a solder bump is preceded by the step of forming a solder dam layer including a solder non-wettable layer on said exposed portions of said under bump metallurgy layer, and wherein said step of applying a chemical etchant is preceded by the step of removing said solder dam layer.
- 7. A method according to claim 6 wherein said step of forming a solder dam layer comprises the step of forming a solder non-wettable layer selected from the group consisting of a titanium layer and a chromium layer.
- 8. A method according to claim 6 wherein said step of forming a solder dam layer further comprises the step of forming a solder wettable layer on said solder non-wettable layer opposite said under bump metallurgy layer.
- 9. A method according to claim 6 wherein said step of forming a solder bump comprises the steps of:
- forming a patterned mask layer on said solder dam layer;
- electroplating solder on said unexposed portion of said under bump metallurgy layer; and
- selectively removing said patterned mask layer.
- 10. A method according to claim 1 wherein said step of forming a solder bump is followed by the step of reflowing said solder bump.
- 11. A method according to claim 10 wherein said step of reflowing said solder bump results in a reaction between said solder bump and said unexposed portion of said under bump metallurgy layer to form an intermetallic region, and wherein said chemical etchant preferentially attacks said under bump metallurgy layer with respect to said intermetallic region.
- 12. A method for forming solder bumps on a microelectronic device having a substrate and a contact pad on said substrate, wherein said contact pad has an exposed surface portion, said method comprising the steps of:
- forming a titanium barrier layer on said contact pad, wherein said barrier layer covers said exposed surface portion of said contact pad and extends over said substrate;
- forming an under-bump metallurgy layer on said barrier layer opposite said substrate, wherein said under-bump metallurgy layer includes a chromium layer;
- forming a solder bump on said under-bump metallurgy layer opposite said exposed surface portion of said contact pad and said barrier layer thereby defining exposed and unexposed surface portions of said under-bump metallurgy layer;
- selectively removing said exposed portion of said under-bump metallurgy layer thereby defining an exposed portion of said barrier layer; and selectively removing said exposed portion of said barrier layer.
- 13. A method according to claim 12 wherein said contact pad comprises a titanium contact pad.
- 14. A method according to claim 12 wherein said step of selectively removing said exposed portion of said under bump metallurgy layer comprises the step of applying a chemical etchant to said under bump metallurgy layer wherein said chemical etchant attacks said under bump metallurgy layer preferentially with respect to said barrier layer and said solder bump.
- 15. A method according to claim 12 wherein said step of selectively removing said exposed portion of said titanium barrier layer comprises the step of applying a titanium etchant to said barrier layer wherein said titanium etchant attacks said barrier layer preferentially with respect to said solder bump and said under bump metallurgy layer.
- 16. A method according to claim 12 wherein said step of forming an under bump metallurgy layer comprises the steps of:
- forming a chromium layer on said barrier layer;
- forming a phased layer of chromium and copper on said chromium layer opposite said barrier layer; and
- forming a copper layer on said phased layer opposite said chromium layer.
- 17. A method according to claim 16 wherein said step of selectively removing said exposed portion of said under bump metallurgy layer further comprises the steps of:
- applying a copper etchant to said exposed portion of said copper layer wherein said copper etchant selectively attacks said copper layer and said copper portion of said phased layer preferentially with respect to said solder bump, said chromium layer, and said titanium barrier layer; and
- applying a chromium etchant to said chromium portion of said phased layer and said chromium layer wherein said chromium etchant selectively attacks said chromium portion of said phased layer and said chromium layer preferentially with respect to said solder bump, said copper layer, and said titanium barrier layer.
- 18. A method according to claim 12 wherein said step of forming a solder bump is preceded by the step of forming a solder dam layer including a solder non-wettable layer on said exposed portions of said under bump metallurgy layer, and wherein said step of selectively removing said exposed portion of said under bump metallurgy layer is preceded by the step of removing said solder dam layer.
- 19. A method according to claim 18 wherein said step of forming a solder dam layer comprises the step of forming a solder non-wettable layer selected from the group consisting of a titanium layer and a chromium layer.
- 20. A method according to claim 18 wherein said step of forming a solder dam layer further comprises the step of forming a solder wettable layer on said solder non-wettable layer opposite said under bump metallurgy layer.
- 21. A method according to claim 18 wherein said step of forming a solder bump comprises the steps of:
- forming a patterned mask layer on said solder dam layer;
- electroplating solder on said unexposed portion of said under bump metallurgy layer; and
- selectively removing said patterned mask layer.
- 22. A method according to claim 12 wherein said step of forming a solder bump is followed by the step of reflowing said solder bump.
- 23. A method according to claim 22 wherein said step of reflowing said solder bump results in a reaction between said solder bump and said unexposed portion of said under bump metallurgy layer to form an intermetallic region.
- 24. A method for forming solder bumps on a microelectronic device having a substrate and a contact pad on said substrate, wherein said contact pad has an exposed surface portion, said method comprising the steps of:
- forming an under bump metallurgy layer on said contact pad, wherein said under bump metallurgy layer covers said exposed surface portion of said contact pad and extends over said substrate;
- forming a solder dam on portions of said under bump metallurgy layer, said solder dam defining an uncovered portion of said under bump metallurgy layer opposite said exposed surface portion of said contact pad, said solder dam comprising a solder non-wettable layer on said under bump metallurgy layer and a solder wettable layer on said solder non-wettable layer opposite said under bump metallurgy layer; and
- forming a solder bump on said uncovered portion of said under bump metallurgy layer opposite said exposed surface portion of said contact pad thereby defining exposed and unexposed surface portions of said under bump metallurgy layer, said solder bump extending onto a portion of said solder dam thereby defining exposed and unexposed portions of said wettable layer.
- 25. A method according to claim 24 further comprising the steps of:
- selectively removing said exposed portion of said solder wettable layer; and
- reflowing said solder bump thereby dissolving said unexposed portion of said solder wettable layer into said solder bump, said reflowed solder bump including said dissolved solder wettable layer and forming a solder ball on said unexposed portion of said under bump metallurgy layer.
- 26. A method according to claim 25 wherein said reflowing step results in a reaction between said solder bump and said exposed portion of said under bump metallurgy thereby forming an intermetallic region.
- 27. A method according to claim 24 wherein said solder wettable layer comprises copper.
- 28. A method according to claim 24 wherein said solder non-wettable layer comprises chromium.
- 29. A method according to claim 24 wherein said contact pad comprises a titanium contact pad.
- 30. A method according to claim 24 wherein the step of forming an under bump metallurgy layer is preceded by the step of forming a titanium barrier layer on said contact pad, wherein said titanium barrier layer covers said exposed surface portion of said contact pad and extends over said substrate.
- 31. A method according to claim 30 further comprising the steps of:
- selectively removing said exposed portion of said solder dam and said under bump metallurgy layer thereby defining an exposed portion of said barrier layer; and
- selectively removing said exposed portion of said barrier layer.
- 32. A method according to claim 31 wherein said step of selectively removing said exposed portion of said under bump metallurgy layer comprises the step of applying a chemical etchant to said under bump metallurgy layer wherein said chemical etchant attacks said under bump metallurgy layer preferentially with respect to said barrier layer and said solder bump.
- 33. A method according to claim 31 wherein said step of selectively removing said exposed portion of said titanium barrier layer comprises the step of applying a titanium etchant to said barrier layer wherein said titanium etchant attacks said barrier layer preferentially with respect to said solder bump and said under bump metallurgy layer.
- 34. A method according to claim 30 wherein said step of forming an under bump metallurgy layer comprises the steps of:
- forming a chromium layer on said barrier layer;
- forming a phased layer of chromium and copper on said chromium layer opposite said barrier layer; and
- forming a copper layer on said phased layer opposite said chromium layer.
- 35. A method according to claim 24 wherein said step of forming a solder bump comprises the steps of:
- forming a patterned mask layer on said solder dam layer;
- electroplating solder on said unexposed portion of said under bump metallurgy layer; and
- selectively removing said patterned mask layer.
Parent Case Info
This application is a continuation, of application Ser. No. 08/407,196, filed Mar. 20, 1995, now abandoned.
Government Interests
The Government of the United States of America may have rights in this invention pursuant to Contract No. 94-50-001 awarded by the Office of the Advanced Research Projects Agency.
US Referenced Citations (27)
Foreign Referenced Citations (10)
Number |
Date |
Country |
55-111127 |
Aug 1980 |
JPX |
55-156339 |
Dec 1980 |
JPX |
56-49543 |
May 1981 |
JPX |
56-66057 |
Jun 1981 |
JPX |
57-11141 |
Mar 1982 |
JPX |
57-73952 |
May 1982 |
JPX |
57-197838 |
Dec 1982 |
JPX |
59-117135 |
Jul 1984 |
JPX |
59-154041 |
Sep 1984 |
JPX |
60-180146 |
Sep 1985 |
JPX |
Non-Patent Literature Citations (4)
Entry |
Yung et al., Electroplated Solder Joints for Flip-Chip Applications, Trans. on Components, Hybrids, and Manufacturing Technology 14:549, No. 3 (1991). |
Yung et al., FLip-Chip Process Utilizing Electroplated Solder Joints, Proceedings of the Technical Conference, p. 1065 (1990). |
Castrucci et al., Terminal Metallurgy System for Semiconductor Devices, IBM Technical Disclosure Bulletin, 9:1805, No. 12 (May 1967). |
Tessier et al., Process Considerations in Fabricating Thin Film Multichip Modules, Proceedings of the Technical Conference, 1:294 (Sep. 1989). |
Continuations (1)
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Number |
Date |
Country |
Parent |
407196 |
Mar 1995 |
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