DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 2a, it depicts a system-in-package (SIP) device 100 according to the first embodiment of the present invention. The SIP device 100 includes a chip package 130, which includes a leadframe 150, a second chip 134 and an encapsulant 136. The leadframe 150 includes a die pad 152 and a plurality of leads 154. Each lead 154 is divided into an inner lead 154a and an outer lead 154b. The die pad 152 and a plurality of leads 154 can be integrally formed. The die pad 152 has an upper surface 151 and a lower surface 153, the upper surface 151 orients against a substrate 122, and the lower surface 153 is opposite to the upper surface 151. The second chip 134, e.g. memory chip, is mounted on the lower surface 153 of the die pad 152 and electrically connected to the inner leads 154a by means of a plurality of bonding wires 138. The encapsulant 136 seals the second chip 134, the bonding wires 138, the lower surface 153 of the die pad 152 and the inner leads 154a, and exposes out the upper surface 151 of the die pad 152 and the outer leads 154b. Since the encapsulant 136 exposes out the upper surface 151 of the die pad 152 and the second chip 134 is mounted on the lower surface 153 of the die pad 152, the heat resulted from the second chip 134 can be dissipated by the die pad 152.
The SIP device 100 further includes the substrate 122, a first chip 124 and an encapsulant 126. The substrate 122 has an upper surface 121 and a lower surface 123 opposite to the upper surface 121. The first chip 124, e.g. processor chip, is mounted on the upper surface 121 of the substrate 122, and is electrically connected to the substrate 122 by means of a plurality of bonding wires 128. The chip package 130 is stacked above the first chip 124.
The SIP device 100 further includes a spacer 142, which is disposed between the first chip 124 and the chip package 130, thereby defining a first predetermined gap between the substrate 122 and the encapsulant 136. The heights of the bonding wires 128 are less than the first predetermined gap. Furthermore, the outer leads 154b of the leadframe 150 of the chip package 130 are mounted and electrically connected to the substrate 122 of the SIP device 100. The encapsulant 126 seals a part of the chip package 130 (which includes the outer leads 154b), the spacer 142, the bonding wires 128, the first chip 124 and the upper surface 121 of the substrate 122, and to expose out the lower surface 123 of the substrate 122 and the upper surface 151 of the die pad 152. Since the encapsulant 126 also exposes out the upper surface 151 of the die pad 152, the heat resulted from the second chip 134 can be directly dissipated to the environment by the die pad 152. It is apparent to one of ordinary skill in the art that the die pad 152 can be replaced by any type of heat sink, or a heat sink (not shown) is additionally assembled on the upper surface 151 of the die pad 152 so as to increase the efficiency of heat dissipation.
Referring to FIG. 2b, it depicts a chip package 130′ of a system-in-package (SIP) device 100 according to an alternative embodiment of the present invention. The die pad 152 has an upper surface 151 and a lower surface 153, the upper surface 151 orients against a substrate 122, and the lower surface 153 is opposite to the upper surface 151. The second chip 134 is mounted on the upper surface 151 of the die pad 152 and electrically connected to the inner leads 154a by means of a plurality of bonding wires 138. The encapsulant 136 seals the second chip 134, the bonding wires 138, the upper surface 151 and the lower surface 153 of the die pad 152 and the inner leads 154a, and to expose out the outer leads 154b.
In addition, the substrate 122 includes a plurality of electrical contacts 146, e.g. solder balls, are disposed the lower surface 123 of the substrate 122, and are adapted to electrically connected to an external electronic device (not shown) or an external circuit board (not shown).
Referring to FIGS. 2a and 2b again, the SIP device 100 further includes a third chip 160, which is stacked on the first chip 124. The SIP device 100 further includes a plurality of bonding wires 162 adapted for electrically connecting the third chip 160 to the substrate 122. The heights of the bonding wires 162 are less than the first predetermined gap. Furthermore, the spacer 142 of the SIP device 100 is further adapted to define a second predetermined gap between the first chip 124 and the encapsulant 136. The SIP device 100 further includes a plurality of bonding wires 164 adapted for electrically connecting the third chip 160 to the first chip 124. The heights of the bonding wires 164 are less than the second predetermined gap.
The SIP device of the present invention is characterized in that a general substrate (e.g. the substrate 32 shown in FIG. 1) of the chip package is replaced with a leadframe so as to have the following advantages. First, the leads of the leadframe of the chip package are electrically connected to the substrate by means of a surface mounting technology (SMT), i.e. the chip package are not electrically connected to the substrate by means of a wire bonding technology. Thus, it is not easy that the encapsulant 126 flushes the leads of the leadframe of the chip package while the encapsulant 126 is formed. Second, it is easy to rework that the leads of the leadframe of the chip package are electrically connected to the substrate by using a surface mounting technology (SMT), and oppositely it is difficult to rework that the chip package are electrically connected to the substrate by using a wire bonding technology. Thus, the present invention can decrease the lost yield. Third, since both encapsulants 126, 136 expose out the upper surface of the die pad and the second chip is mounted on the lower surface of the die pad, the heat resulted from the second chip can be directly dissipated to the environment by the die pad, thereby decrease the work temperature of the second chip and not decrease the efficiency of the second chip. Fourth, compared with the prior art, the electrical test of the second chip of the present invention is not required to wait for the SIP device which is finished, i.e. the second chip can be directly electrically tested after the second chip is packaged in the chip package. Thus, the unserviceable second chip can be sieved out in advance so as to decrease the lost yield of the whole SIP device.
Referring to FIG. 3, it depicts a system-in-package (SIP) device 200 according to the second embodiment of the present invention. The SIP device 200 includes a chip package 230, which includes a leadframe 250, a second chip 234 and an encapsulant 236. The leadframe 250 includes a die pad 252 and a plurality of leads 254. Each lead 254 is divided into an inner lead 254a and an outer lead 254b. The die pad 252 has an upper surface 251 and a lower surface 253, the upper surface 251 orients against a substrate 222, and the lower surface 253 is opposite to the upper surface 251. The second chip 234, e.g. memory chip, is mounted on the lower surface 253 of the die pad 252 and electrically connected to the inner leads 254a by means of a plurality of bonding wires 238. The encapsulant 236 seals the second chip 234, the bonding wires 238, the lower surface 253 of the die pad 252 and the inner leads 154a, and exposes out the upper surface 251 of the die pad 252 and the outer leads 254b.
The SIP device 200 further includes the substrate 222, a first chip 224 and an encapsulant 226. The substrate 222 has an upper surface 221 and a lower surface 223 opposite to the upper surface 221. The first chip 224, e.g. processor chip, is mounted on the substrate 222, and is electrically connected to the substrate 222 by means of a plurality of metallic bumps 228. The chip package 230 is stacked above the first chip 224. Furthermore, the outer leads 254b of the leadframe 250 of the chip package 230 are mounted and electrically connected to the substrate 222 of the SIP device 200. The encapsulant 226 seals a part of the chip package 230 (which includes the outer leads 254b), the first chip 224 and the upper surface 221 of the substrate 222, and exposes out the lower surface 223 of the substrate 222 and the upper surface 251 of the die pad 252. The substrate 222 includes a plurality of electrical contacts 246, e.g. solder balls, are disposed the lower surface 223 of the substrate 222 and are adapted to electrically connected to an external electronic device (not shown) or an external circuit board (not shown).
Referring to FIG. 4, it depicts a system-in-package (SIP) device 300 according to the third embodiment of the present invention. The SIP device 300 in the third embodiment is substantially similar to the SIP device 200 in the second embodiment, wherein the similar elements are designated with the similar reference numerals. The SIP device 300 further. includes a third chip 360, which is stacked on the first chip 324. The SIP device 300 further includes a spacer 342, which is disposed between the first chip 324 and the chip package 330, thereby defining a predetermined gap between the substrate 322 and the encapsulant 336. The SIP device 300 further includes a plurality of bonding wires 362 adapted for electrically connecting the third chip 360 to the substrate 322. The heights of the bonding wires 362 are less than the predetermined gap.
Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.
Patent Application
20070284715
