BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1A to 1D show a conventional fabrication process of a carrier board structure with a semiconductor chip embedded therein;
FIG. 2 is a sectional view of another conventional carrier board structure with a semiconductor chip embedded therein;
FIGS. 3A to 3E show a fabrication process of a carrier board structure with a semiconductor chip embedded therein according to a first embodiment of the present invention; and
FIG. 4 is a sectional view of a carrier board structure with a semiconductor chip embedded therein according to a second embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
The present invention relates generally to a carrier board structure, and more particularly to a carrier board structure with a semiconductor chip embedded therein. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
FIGS. 3A to 3E show a fabrication process of a carrier board structure with a semiconductor chip embedded therein according to a first embodiment of the present invention.
As shown in FIG. 3A, a carrier board 20 with a first surface 20a and a second surface 20b opposed to the first surface 20a is provided and a circular or rectangular cavity 21 penetrating through the first and second surfaces 20a and 20b of the carrier board 20 is formed in the carrier board 20. The cavity 21 has a chamfer 210, and the chamfer 210 is a full chamfer. In the present embodiment, the cavity 21 can be formed by cutting, punching or laser ablating application.
As shown in FIG. 3B, at least a semiconductor chip 22 is disposed in the cavity 21. Due to the chamfer 210, the semiconductor chip 22 is easy to be disposed in the cavity 21. An adhesion board (not shown) can be disposed on the second surface 20b of the carrier board 20 and can be removed in subsequent processes. The semiconductor chip 22 has an active surface 22a and a non-active surface 22b opposed to the active surface 22a, wherein the active surface 22a of the semiconductor chip 22 has a plurality of electrode pads 220. In the present embodiment, the semiconductor chip 22 is disposed in the cavity 21 through its non-active surface 22b.
As shown in FIG. 3C, an adhesion material 23 such as a resin material or a colloid is filled in the gap between the cavity 21 and the semiconductor chip 22. After the adhesion material 23 is cured, the semiconductor chip 22 is fixed in the cavity 21. In the present embodiment, the chamfer 210 of the cavity 21 makes the gap between the cavity 21 and the semiconductor chip 22 have a funnel shape with a wider cavity at the top thereof. As a result, the adhesion material 23 can smoothly flow into the cavity 21 and firmly and evenly fill the cavity 21 so as to eliminate the popcorn problem during subsequent heat circulation process caused by residual air or voids. Meanwhile, since there is a much big distance between the lateral sides of the semiconductor chip 22 and the cavity 21, thermal stress generated by different coefficients of thermal expansion can be prevented from causing the lateral side of the cavity 21 to press against the lateral side of the semiconductor chip 22, thereby avoiding the damage of the semiconductor chip 22. Also, too big thermal stress between the lateral sides of the semiconductor chip 22 and the cavity 21 can be avoided so as to facilitate the subsequent circuit build-up process.
As shown in FIG. 3D, a first dielectric layer 24 is formed on the first surface 20a of the carrier board 20 and the active surface 22a of the semiconductor chip 22, and a second dielectric layer 25 is formed on the second surface 20b of the carrier board 20 and the non-active surface 22b of the semiconductor chip 22. The first dielectric layer 24 has a plurality of openings 240 so as to expose the electrode pads 220 of the semiconductor chip 22. The first and second dielectric layers 24,25 may be made of materials such as Epoxy resin, Polyimide, Cyanate ester, Glass fiber, BT (Bismaleimide triazine), PP (Polypropylene), ABF and a mixture of epoxy resin and glass fiber.
As shown in FIG. 3E, a circuit build-up structure 26 is further formed on surfaces of the first dielectric layer 24 and the second dielectric layer 25. The circuit build-up structure 26 comprises a dielectric layer 260, a circuit layer 261 stacked on the dielectric layer 260 and conductive structures 262 formed in the dielectric layer 260. Parts of the conductive structures 262 is electrically connected to the electrode pads 220 of the semiconductor chip 22 and a plurality of electrically connecting pads 263 are formed on surface of the circuit build-up structure 26. The circuit build-up structure 26 respectively on the first and second dielectric layers 24, 25 is electrically connected through at least a plating through hole 29.
A solder mask layer 28 is formed on surface of the circuit build-up structure 26, which has a plurality of openings 280 so as to expose the electrically connecting pads 263 on the surface of the circuit build-up structure 26.
Referring to FIG. 4, another embodiment of the present invention is shown. The chamfer 210′ of the cavity 21 of the present embodiment is a half chamfer, that is, instead of obliquely cutting the entire cavity 21 as a full chamfer, only a part of the cavity is obliquely cut and the other part of the cavity is remained at vertical state. Through the half chamfer, the semiconductor chip 22 can also be easily disposed in the cavity 21 and the adhesion material 23 can be evenly and firmly filled in the cavity 21 without the generation of air bubble or voids. Thermal stress can be prevented from causing the lateral side of the cavity 21 to press against the lateral side of the semiconductor chip 22 so as to avoid the damage of the semiconductor chip 22. Also, too big thermal stress between the lateral sides of the semiconductor chip 22 and the cavity 21 can be avoided so as to facilitate the subsequent circuit build-up process.
Through the above fabrication process, a carrier board structure with a semiconductor chip embedded therein is obtained, which comprises: a carrier board 20 having at least an cavity 21 with a chamfer 210, at least a semiconductor chip 22 disposed in the cavity 21, and an adhesion material 23 filled the gap between the cavity 21 and the semiconductor chip 22 so as to fix the semiconductor chip 22 in the cavity 21. The carrier board 20 has a first surface 20a and a second surface 20b opposed to the first surface 20a, and the cavity 21 of the circuit board 20 penetrates through the first and second surfaces 20a and 20b. The chamfer 210 of the cavity 21 can be a full chamfer or a half chamfer. The semiconductor chip 22 has an active surface 22a and a non-active surface 22b, wherein the active surface 22a of the semiconductor chip 22 has a plurality of electrode pads 220.
In the present embodiment, the carrier board structure further comprises a first dielectric layer 24 formed on the first surface 20a of the carrier board 20 and the active surface 22a of the semiconductor chip 22, and a second dielectric layer formed on the second surface 20b of the carrier board 20 and the non-active surface 22b of the semiconductor chip 22. In addition, a circuit build-up structure 26 is formed on the first and second dielectric layers 24,25. A solder mask layer 28 is formed on surface of the circuit build-up layer 26. The solder mask layer 28 has a plurality of openings 280 so as to expose the electrically connecting pads 263 formed on surface of the circuit build-up structure 26.
Through the chamfer formed in the cavity of the carrier board, the semiconductor chip can easily be disposed in the cavity.
In addition, the funnel-shaped chamfer of the cavity allows the adhesion material to be firmly and evenly filled in the cavity of the carrier board so as to avoid the generation of air bubble or voids caused by uneven filling or insufficient filling of the adhesion material. As a result, the popcorn problem caused in a subsequent heat circulation process by the residual air and voids can be avoided and accordingly the process reliability is increased.
Furthermore, the chamfer of the cavity leads to a big distance between the lateral side of the semiconductor chip and the lateral side of the cavity, which is helpful to prevent the thermal stress generated by different coefficients of thermal expansion from damaging the semiconductor chip by making the lateral side of the cavity press against the lateral side of the semiconductor chip.
Moreover, the chamfer of the cavity can prevent the happening of delamination of the dielectric layer from the cavity because of big thermal stress between the lateral side of the semiconductor chip and the lateral side of the cavity.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
Patent Application
20080054443
