Component and method of manufacturing a component using an ultrathin carrier

Abstract

A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

Description

TECHNICAL FIELD

Embodiments of the invention relate generally to a method of manufacture a component, and in particular embodiments, to a method of manufacture a component using an ultrathin wafer.

BACKGROUND

Processing ultrathin wafers is difficult because they break easier than regular wafers during dicing. Moreover, the separated chips may break during the pick-up process or while wire bonded.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the present invention, a method for manufacturing a component comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

In accordance with an embodiment of the present invention, a method for manufacturing a component comprises forming a plurality of components on a carrier and forming a metal pattern on a backside of the carrier, the metal pattern comprising free standing metal blocks separated by spaces. The method further comprises forming the component by separating the carrier along the spaces.

In accordance with an embodiment of the present invention, a method for manufacturing a wafer comprises forming kerf regions and chips on a first main surface of the wafer and forming a metal pattern on a second main surface of the wafer, wherein the metal pattern covers the second main surface of the wafer except over regions corresponding to the kerf regions.

In accordance with an embodiment of the present invention, a packaged semiconductor device comprises a carrier and a component disposed on the carrier, the component comprising a substrate having a thickness of about 20 μm or less and a metal block comprising a thickness of about 20 μm or more. The packaged semiconductor device further comprises a connection layer connecting the carrier and the component, and a conductive wire or a conductive clip connecting a component contact pad of the component with a carrier contact pad of the carrier. The packaged semiconductor device finally comprises an encapsulant encapsulating the component.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a flow chart of an embodiment of a method to manufacture a component package;

FIG. 2 shows an embodiment of a top surface of a patterned photoresist on the backside of a carrier;

FIG. 3a shows an embodiment of a top surface of a patterned metal layer on the backside of a carrier;

FIG. 3b shows an embodiment of a cross-section of a patterned metal layer on the backside of a carrier;

FIG. 4 shows an embodiment of a singulated component having a metal block on the backside;

FIG. 5a shows an embodiment of a packaged component comprising a metal block on the backside;

FIG. 5b shows an embodiment of a packaged component comprising a metal block on the backside;

FIG. 6a shows an embodiment of a backside metal pattern arrangement; and

FIG. 6b shows an embodiment of a backside metal pattern arrangement.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to embodiments in a specific context, namely a thin wafer processing method and device. The invention may also be applied, however, to other carrier processing methods and devices.

A safe and secure processing of conventional wafers and chips typically requires a silicon thickness of about 60 μm or more for the substrate of the wafers or chips. Processing of wafers or chips below this thickness is difficult because there are serious handling problems in front end and back end processes. For example, when the chips are removed from the sawing foil (pick-up) they may break or fracture due to their thin silicon substrate. Moreover, when the chips are wire bonded they may break or crack due to the mechanical pressure and the ultrasound applied to the chips. A 100% loss of the processed chips may be experienced.

Embodiments of the invention provide mechanical stabilization of ultra-thin carriers and components. Embodiments of the invention further provide an excellent electrical and thermal contact on the backside of a component. Embodiments of the invention provide a void free backside contact for a component. An advantage of the mechanical stabilization of the component and the carrier is a reliable handling of the component and the carrier with an ultra-thin substrate. A further advantage of components with ultra-thin substrate is that the electrical and thermal parameters are improved relative to components with regular sized substrate. For example, the electrical resistance of the components may be reduced because of the thinner substrate.

FIG. 1 shows a flow chart 100 of an embodiment of a method for manufacturing a packaged electric component. In a first step 110, a carrier is mounted on a support carrier. The carrier may be a workpiece, a substrate, a wafer, or a printed circuit board (PCB).

The carrier may be a semiconductor substrate such as silicon or germanium, or a compound substrate such as SiGe, GaAs, InP, GaN or SiC. Alternatively, the carrier comprises other materials. The substrate may be a single crystal silicon or a silicon-on insulator (SOI). The substrate may be doped or un-doped.

One or more interconnect metallization layers may be arranged on the carrier. A passivation layer is disposed on the interconnect metallization layers forming a top surface or a first main surface of the carrier. The passivation layer may electrical isolate and structure component contacts or component contact pads of the components of the carrier. The passivation layer may comprise SiN, for example. The first main surface is located on the front side of the carrier. The carrier comprises a bottom surface or a second main surface. The second main surface is located on the backside of the carrier.

In one embodiment, the first main surface is the surface where the active areas are predominately disposed and the second main surface is the surface which is active area free or which is predominately active area free.

The carrier comprises a plurality of components such as chips or dies. The component may comprise a discrete device such as a single semiconductor device or an integrated circuit (IC). For example, the component may comprise a power semiconductor device such as a bipolar transistor, an insulated gate bipolar transistor (IGBT), a power MOSFET, a thyristor or a diode. Alternatively, the component may be resistor, a protective device, a capacitor, a sensor or a detector, for example.

The carrier comprises kerfs, kerf lines or kerf regions separating and structuring the components. The carrier is separated, singulated or cut along the kerf lines into single components. The carrier comprises a grid or a pattern of kerf lines in x-direction and in y-directions. The kerf lines are the region along which the components are separated from each other.

The carrier may be attached to a support carrier. The support carrier may be a glass carrier. Alternatively, the support carrier may be semiconductive carrier such as a silicon carrier. In one embodiment, the first main surface of the carrier is glued to the glass carrier so that the second main surface of the carrier is exposed.

In step 115, the carrier is thinned, that is, the thickness of the backside of the carrier is reduced. For example, the substrate is thinned to a thickness of about less than about 40 μm or to a thickness of about less than about 20 μm. Alternatively, the substrate is thinned to a thickness of about 10 μm to about 20 μm. The substrate may be thinned by grinding or abrasive cutting. A mercury cleaning which removes excess glue residues after mounting the carrier to the support carrier may not be carried out because the cleaning step may lead to edge breakings of the component during grinding.

In step 120, the carrier is smoothened and cleaned. For example, the carrier is smoothened applying a wet etch such as an HNO₃ and a cleaned applying a water cleaning.

In step 125, an optional stress relaxation is carried out. The stress relaxation may be advantageous because the substrate thickness (after thinning) may be in a same or similar dimension range as the interconnect metallization layers on the front side of the carrier and the CTEs of the substrate and the interconnect metallization layers are different. The stress relaxation may be carried out applying a Cryo process. For example, the Cryo process may be carried out at temperatures of about −70° C.

In step 130, the backside of the carrier is aligned to the front side of the carrier. In one embodiment the front side alignment mark is copied, imaged, mapped or reproduced on the backside of the carrier. Alternatively, the backside of the carrier is aligned with the front side alignment mark. For example, the carrier can be aligned by “seeing through” the substrate of the carrier.

In step 135, optionally an under-layer is formed on the backside of the carrier. The under-layer may be a metal layer. For example, the under-layer may be aluminum (Al) or aluminum alloy, titanium (Ti) or titanium alloy, or a combination thereof. Alternatively, the under-layer may comprise copper (Cu), nickel vanadium (NiV) or silver (Ag). The under-layer may be a layer stack. For example, the under-layer may comprise a first layer adjacent to the carrier and a second layer disposed on the first layer. The first layer may be an adhesion layer and the second layer may be barrier layer. In one example, the first layer comprises an aluminum or aluminum alloy (e.g., 200 nm thick) and the second layer comprises titanium or titanium alloy (e.g., 200 nm thick). The under-layer may be formed by sputtering. Alternatively other deposition processes may be used such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or evaporation.

A seed layer is formed over the under-layer. The seed layer may be a metal layer. For example, the seed layer may be aluminum (Al) or aluminum alloy, copper (Cu) or copper alloy, or a combination thereof. The seed layer may be formed by sputtering. Alternatively other deposition processes may be used such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or evaporation. In one embodiment sputtering is carried out at low temperatures, e.g., at temperatures of about 100° C. In one embodiment the under-layer and the seed layer are formed in a single process forming a layer stack providing a contact, a barrier and a seed layer.

In step 140, a photoresist is formed over the seed layer. The photoresist may be formed by spin-coating. The photoresist may be a resists which enables resist thicknesses larger than about 20 μm. Then, in step 145 the photoresist is patterned and developed. In one embodiment the photoresist is patterned and developed such that the photoresist pattern mirrors or maps the kerf regions or kerf lines on the front side of the carrier. The photoresist is removed over the backside of the components and remains standing over the kerf regions or kerf lines. In one embodiment patterning of the photoresist forms photoresist ridges, fins or bars. The ridges, fins or bars may comprise the form of frames or cross-like bars. The ridges, fins or bars may comprise the form of a circumference of a square or a rectangular. Alternatively, the ridges, fins or bars may comprise other forms. In one embodiment the removed portions of the photoresist may comprise the form of panels, squares, rectangles, checks, or blocks. Alternatively, the removed portions of the photoresist may comprise other forms. FIG. 2 shows a detail of an embodiment of a photoresist pattern on the backside of the carrier. Photoresist ridges, fins or bars 210 remain standing while the photoresist is removed from the areas 220. In one embodiment, the ridges, fins or bars 210 comprise the same thickness d₁ in x-direction and in y-direction. The carrier may be cleaned to remove unnecessary organic deposits. For example, the carrier may be cleaned with an O₂ plasma.

In step 150, a metal pattern is formed. In one embodiment the metal pattern or metal layer is formed by galvanic plating. The carrier is immersed in a metal bath and the metal pattern (metal blocks) are electro plated from and over the seed layer between the photoresist ridges, fins and bars. For example, the carrier is immersed in a copper (Cu) bath. The metal thickness is adjusted by leaving the carrier a predetermined time in the metal bath. For example, the metal thickness of the copper blocks may be about 20 μm to about 50 μm or about 20 μm to about 100 μm. The metal blocks may be thicker than the substrate of the components. In one embodiment the metal is thicker than the substrate when the metal block is not only configured to be an electrical contact but also configured to be a heat-sink.

An advantage of the electroplating process is that a thick metal pattern can be formed in a comparably short period of time. A further advantage is that the electroplating process provides void free metal blocks and void free interface to the component carrier.

FIG. 3a shows a detail of a top view of an embodiment of a metal pattern or metal layer (e.g., copper) on the backside of the carrier. The metal blocks 320 are spaced apart from each other by the resist ridges, bars or fins 310. FIG. 3b shows a detail of a cross-sectional view of the metal pattern on the backside of the carrier. The resist ridges, fins or bars 310 are placed between the metal blocks 320 over a substrate 300. A seed layer and/or under-layer may be disposed between the substrate 300 and the resist bars/metal blocks 310, 320.

In an embodiment the metal pattern is formed by other fast depositing processes. For example, the metal pattern may be formed by a screen printing process applying an inkjet printer or stencil printing process.

In step 155, the remaining photoresist layer is removed. For example, the photoresist frame or the photoresist ridges, fins or bars are removed. The photoresist is removed by organic liquid media.

In step 160, the support carrier and the carrier are placed on a dicing foil. Then the support carrier is removed from the carrier. In step 165, the components are separated, singulated or cut from the carrier. In one embodiment the carrier is singulated using a dicing laser. In one embodiment the carrier is singulated applying a plasma etch using the metal blocks as hard mask. Alternatively the carrier is singulated using a dicing saw. An embodiment of a detail of a component 410 with a backside metal 420 is shown in FIG. 4. FIG. 4 shows a distance d of a rim or gap 430 between the circumference of the component 410 and the circumference of the backside metal block 420. In one embodiment it is advantages that the distance d₂ is as small as possible, e.g., between about 5 μm and about 0 μm.

In step 170, the separated individual components are flipped and assembled on a component carrier. The component carrier may be a workpiece, a substrate, a wafer, or a printed circuit board (PCB). In one embodiment the component carrier is a leadframe comprising a metal such as copper (Cu) or a copper alloy, nickel (Ni) or nickel alloy, silver (Ag) or silver alloys, or a combination thereof

The component is attached to the component carrier at the component placement area. For example, the metal layer or metal block on the backside of the component is attached to the top surface of the component carrier. In one embodiment the metal layer is bonded to the top surface of the component carrier using a soldering, eutectic bonding or an epoxy bonding. Alternatively, the second main surface is bonded or glued to the top surface of the carrier using an adhesive tape, a solder paste or a solder. In one embodiment the connection between the component and the component carrier is an electrical connection. Alternatively, the connection is an insulating barrier.

In step 175, the component is bonded to the component carrier. For example, component contacts or component contact pads disposed on a top surface or first main surface of the component are bonded to component carrier contacts or component carrier contact pads of the component carrier. The contacts of the component are wire bonded, ball bonded, clip bonded or otherwise bonded to the contacts of the component carrier. The wires or conductive clips comprise a metal such as aluminum (Al), copper (Cu), silver (Ag) or gold (Au).

For example, a first component contact disposed on the first main surface of the component is electrically connected to a first component carrier contact. The component may further comprise a second component contact and/or a third component contact on the first main surface. Alternatively, the component may have other contact pad arrangements on its first main surfaces.

At step 180, the component is encapsulated with a molding compound. In one embodiment the encapsulation material may be a molding compound. The molding compound may comprise a thermoset material or a thermoplastic material. The molding compound may comprise a coarse grained material. In one embodiment the molding compound may be applied to encapsulate the component and at least portions of the component carrier. Alternatively, the encapsulation material may be a laminate material such as a prepreg material.

Optionally, when several of components are placed on the component carrier, the encapsulated component/component carrier may be diced into packaged electric components each comprising a component. For example, the individual packaged electric components are singulated using a dicing saw.

FIG. 5a shows a packaged electric component comprising a component 500 having a thickness d₃ and a metal block 540 having a thickness d₄, wherein d₃ is substantially the same as d₄. The metal block (e.g., copper) 540 may be soldered to the component carrier (e.g., lead frame) 590. One or more component contact pads 512 of the component 500 are connected via wires or conductive clips 514 to one or more component carrier contact pads 592 of the component carrier 590.

FIG. 5b shows a packaged electric component comprising a component 500 having a thickness d₅ and a metal block 540 having a thickness d₆, wherein d₆ is substantially larger than d₅. The metal block 540 may comprise a heat sink. The metal block (e.g., copper) 540 may be soldered to the component carrier (e.g., lead frame) 590. One or more component contact pads 512 of the component 500 are connected via wires or conductive clips 514 to one or more component carrier contact pads 592 of the component carrier 590.

FIG. 6a shows the backside metal pattern arrangement 600 in a flipped position. A wafer 610 is glued or connected to a glass carrier 620. The wafer 610 is connected to the glass carrier 620 on its front side. In this embodiment an alignment mark is arranged on its backside of the wafer 610. A seed layer or a seed layer together with an under-layer 630 is disposed directly adjacent to the wafer 610. The seed layer (together with the under-layer) 630 may comprise a metal layer stack. The seed layer 630 may cover the entire backside of the wafer 610. A metal pattern 640 (e.g., copper) is arranged over the seed layer/under-layer on the backside of the wafer 610. The wafer (e.g., substrate of the wafer) 610 comprises a thickness d₇ and the metal pattern 640 comprises a thickness d₈. The thickness d₈ is larger than the thickness d₇. The metal pattern 640 is structured by a resist pattern 650.

FIG. 6b shows the backside metal pattern arrangement 600 after it is placed on a dicing foil 660. The resist pattern 650 and the glass carrier 620 have been removed. FIG. 6b shows the backside metal pattern arrangement 600 wherein the metal blocks 640 are separated by spaces or air gaps 670. The spaces or air gaps 670 are replacing the removed resist pattern 650. As FIG. 6b shows the wafer 610 is cut with a cutting tool 680 in and along the spaces or air gaps 670. The cutting tool 680 cuts through the wafer 610 and the under-layer/seed layer 630 but not through the metal pattern/blocks 640. The cutting tool 680 may be a dicing laser.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A method for manufacturing a component, the method comprising: forming a plurality of components disposed on a front side of a first carrier comprising a semiconductor substrate, the plurality of components being separated from each other by kerf regions;attaching the front side of the first carrier on a second carrier;forming a planar metal pattern on a backside of the first carrier, wherein the planar metal pattern covers the backside of the first carrier except over regions corresponding to the kerf regions, and wherein the planar metal pattern comprises free standing metal blocks separated by the regions corresponding to the kerf regions;removing the second carrier and placing the first carrier on a sawing foil; andseparating the component from the first carrier,wherein forming the planar metal pattern comprises forming a metal seed layer and electro-plating a metal of the planar metal pattern on the metal seed layer, and forming an under-layer between the seed layer and a substrate of the component, wherein the under-layer comprises a metal adhesion layer and a metal barrier layer.

2. The method according to claim 1, wherein the planar metal pattern comprises copper (Cu).

3. The method according to claim 1, wherein the substrate of the component and the planar metal pattern comprises about the same thickness.

4. The method according to claim 1, wherein the substrate of the component comprises a thickness of about 40 μm or less, and wherein the planar metal pattern comprises a thickness of about 20 μm or more.

5. The method according to claim 1, wherein separating the component from the first carrier comprises laser cutting the first carrier along the regions.

6. A method for manufacturing a component, the method comprising: providing a first carrier with a first main surface at a front side of the first carrier and a second main surface at a backside of the first carrier;disposing a plurality of components at the front side of the first carrier;attaching the first main surface of the first carrier to a second carrier;forming a planar patterned metal layer over the second main surface of the first carrier, the planar patterned metal pattern comprising free standing metal blocks separated by spaces;removing the second carrier and placing the first carrier on a sawing foil; andseparating the component from the first carrier along the spaces,wherein forming the planar patterned metal layer comprises forming a metal seed layer and plating a metal layer over the seed layer, and forming an under-layer between the metal seed layer and a substrate of the component, wherein the under-layer comprises a metal layer stack of aluminum and titanium, and wherein the seed layer comprises the same material as the planar patterned metal layer.

7. The method according to claim 6, wherein the first carrier is thinned at the backside before the planar patterned metal layer is formed.

8. The method according to claim 6, wherein forming the planar patterned metal layer comprises forming a photoresist over the seed layer.

9. The method according to claim 6, wherein the substrate of the component comprises a thickness of about 40 μm or less, and wherein the planar patterned metal layer comprises a thickness of about 20 μm or more.

10. The method according to claim 6, wherein separating the component from the first carrier comprises laser cutting the first carrier.

11. The method according to claim 6, further comprising placing the component on a leadframe, and encapsulating the component and at least a portion of the leadframe.

12. The method according to claim 11, wherein placing the component on the leadframe comprises wire bonding or clip bonding the component to the leadframe.

13. A method of manufacturing a wafer, the method comprising: forming kerf regions and chips on a first main surface of the wafer;forming a planar metal pattern on a second main surface of the wafer, wherein the planar metal pattern covers the second main surface of the wafer except over regions corresponding to the kerf regions, and wherein the planar metal pattern comprises free standing metal blocks separated by the regions corresponding to the kerf regions, wherein forming the planar metal pattern comprises forming a metal seed layer and electro-plating a metal of the planar metal pattern on the metal seed layer; andforming an under-layer between the seed layer and a substrate of the wafer, wherein the under-layer comprises a metal adhesion layer and a metal barrier layer.

14. The method according to claim 13, wherein the planar metal pattern comprises copper (Cu).

15. The method according to claim 13, wherein forming the planar metal pattern comprises forming the metal seed layer in a metal bath and patterning a photoresist over the seed layer.