Claims
- 1 through 131. cancelled.
- 132. A three dimensional nonvolatile device array, comprising:
a plurality of vertically separated device levels, each level comprising an array of TFT EEPROMs, each TFT EEPROM comprising a channel, source and drain regions, and a charge storage region adjacent to the channel region; a plurality of bit line columns in each device level, each bit line contacting the source or the drain regions of the TFT EEPROMs; a plurality of word line rows in each device level; and at least one interlayer insulating layer located between the device levels.
- 133. The array of claim 132, wherein:
in at least one device level, the bit line columns are disposed on an opposite side of TFT EEPROM channels from the word line rows; the channel of each TFT EEPROM comprises amorphous silicon or polysilicon; the columns of bit lines extend substantially perpendicular to a source-channel-drain direction of the TFT EEPROMs; each word line contacts the control gates of the TFT EEPROMs or each word line acts as a control gate of the TFT EEPROMs, and the rows of word lines extend substantially parallel to the source-channel-drain direction of the TFT EEPROMs; and word lines are self aligned to the control gates of the array of TFT EEPROMs and the word lines are self aligned to the channel and the charge storage regions of the TFT EEPROMs located below the respective word lines.
- 134. The array of claim 133, wherein each charge storage region comprises an ONO dielectric film or an insulating layer containing conductive nanocrystals.
- 135. The array of claim 133, wherein each charge storage region comprises:
a tunnel dielectric above the channel; a floating gate above the tunnel dielectric; and a control gate dielectric above the floating gate.
- 136. The array of claim 133, further comprising:
sidewall spacers located adjacent to sidewalls of the control gates of the TFT EEPROMs, wherein the sidewall spacers have approximately the same height as the control gates; and an intergate insulating layer which is located between the sidewall spacers above the source and drain regions of the TFT EEPROMs in each device layer, and wherein the intergate insulating layer has approximately the same height as the sidewall spacers.
- 137. The array of claim 136, wherein:
the word lines are located on the sidewall spacers and on the intergate insulating layer in each device level; and the word lines contact the respective TFT EEPROM control gates through an opening between the sidewall spacers.
- 138. The array of claim 137, wherein the bit lines in each device level comprise rails which extend under the intergate insulating layer.
- 139. The array of claim 138, wherein:
the rails comprise silicide layers over doped semiconductor regions; and the doped semiconductor regions comprise the TFT EEPROM source and drain regions in areas where the doped semiconductor regions are located adjacent to the TFT EEPROM channels.
- 140. The array of claim 132, wherein each control gate comprises:
a first portion contacting the charge storage region; and a second portion above the first portion; wherein the first and the second gate portions comprise separately deposited layers.
- 141. The array of claim 132, further comprising word line contacts and bit line contacts which connect the word lines and the bit lines with peripheral circuits located in a semiconductor substrate below the first device level of the array.
- 142. The array of claim 141, wherein the word line and the bit line contacts extend between plural device layers.
- 143. The array of claim 132, wherein:
each memory cell comprises a TFT EEPROM; and each memory cell size per bit is about (2F2)/N, where F is a minimum feature size and N is a number of device layers in a third dimension and where N>1.
- 144 through 150. cancelled.
- 151. A three dimensional memory array, comprising:
a plurality of vertically separated device levels, each level comprising an array of TFT EEPROMs, each TFT EEPROM comprising:
a channel; a source; a drain; a tunneling dielectric located above the channel; a floating gate located above the tunneling dielectric; sidewall spacers located adjacent to the floating gate sidewalls; a word line located above the floating gate; and a control gate dielectric located between the control gate and the floating gate; wherein
the control gate dielectric is located above the sidewall spacers; and the source, the drain and the channel are formed in a polysilicon active layer, which is located above an interlayer insulating layer, such that the EEPROM comprises a TFT; a plurality of bit line columns in each device level, each bit line contacting the source or the drain regions of the TFT EEPROMs, and the columns of bit lines extending substantially perpendicular to a source-channel-drain direction of the TFT EEPROMs; a plurality of word line rows in each device level, and the rows of word lines extending substantially parallel to the source-channel-drain direction of the TFT EEPROMs; and at least one interlayer insulating layer located between the device levels.
- 152. The array of claim 151, wherein:
the word lines are self aligned to the channels and the floating gates of the TFT EEPROMs; and the bit lines in each device level comprise rails which extend under the word lines.
- 153 through 482. cancelled.
Parent Case Info
[0001] This application is a continuation-in-part of U.S. application Ser. No. 09/801,233, filed on Mar. 6, 2001, which is a continuation-in-part of U.S. application Ser. No. 09/745,125, filed on Dec. 22, 2000, both of which are incorporated by reference in their entirety. This application is also a continuation-in-part of U.S. application Ser. No. 09/639,579 filed on Aug. 14, 2000, which is incorporated by reference in its entirety. This application is also a continuation-in-part of U.S. application Ser. No. 09/639,702 filed on Aug. 14, 2000, which is incorporated by reference in its entirety. This application is also a continuation-in-part of U.S. application Ser. No. 09/639,749 filed on Aug. 14, 2000, which is incorporated by reference in its entirety. This application also claims benefit of priority of provisional application 60/279,855 filed on Mar. 28, 2001, which is incorporated by reference in its entirety.
Provisional Applications (1)
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60279855 |
Mar 2001 |
US |
Divisions (1)
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Number |
Date |
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Parent |
09927648 |
Aug 2001 |
US |
Child |
10842008 |
May 2004 |
US |
Continuation in Parts (5)
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Date |
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09801233 |
Mar 2001 |
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Child |
10842008 |
May 2004 |
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Parent |
09745125 |
Dec 2000 |
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Child |
09801233 |
Mar 2001 |
US |
Parent |
09639579 |
Aug 2000 |
US |
Child |
09927648 |
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US |
Parent |
09639702 |
Aug 2000 |
US |
Child |
09927648 |
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US |
Parent |
09639749 |
Aug 2000 |
US |
Child |
09927648 |
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US |