Patent Application
20240265854
One or more embodiments of the present disclosure relate to a display device and a method of manufacturing the same.
With the advancement of the information society, the demand for a display device in various forms and for displaying an image is increasing. A display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and/or a light-emitting display panel. A light-emitting display device may include an organic light-emitting display device including an organic light-emitting diode element as a light-emitting element, an inorganic light-emitting display device including an inorganic semiconductor element as a light-emitting element, or an ultra-small light-emitting diode element (or micro light-emitting diode element) as a light-emitting element.
Recently, a head mounted display including a light-emitting display device has been developed. The head mounted display (HMD) is a spectacle-type monitor device of virtual reality (VR) and/or augmented reality, for example worn in a form of glasses or a helmet to form a focus point at a distance close to user's eyes.
A high-resolution ultra-small light-emitting diode display panel including a micro light-emitting diode element is applied to the HMD. When the ultra-small light-emitting diode element emits light of a single color, in order for an ultra-small light-emitting diode display panel to display various colors, a wavelength conversion layer that converts a wavelength of light emitted from the ultra-small light-emitting diode element may be essential (e.g., may be needed).
Aspects and features of embodiments of the present disclosure include a display device that does not require a wavelength conversion layer by including an ultra-small light-emitting diode element emitting (e.g., configured to emit) light of a red wavelength band, an ultra-small light-emitting diode element emitting (e.g., configured to emit) light of a green wavelength band, and an ultra-small light-emitting diode element emitting (e.g., configured to emit) light of a blue wavelength band, and a method of manufacturing the same.
However, embodiments of the present disclosure are not limited to those set forth herein. The above and other embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.
According to one or more embodiments of the present disclosure, there is provided a display device including a substrate, a plurality of pixel electrodes provided on the substrate and spaced apart from each other, a plurality of light-emitting elements on the plurality of pixel electrodes, respectively, and a common electrode layer on the plurality of light-emitting elements and to which a common voltage is applied. The plurality of light-emitting elements include a first light-emitting element that is configured to emit first light according to a first driving current and a second light-emitting element that is configured to emit second light according to a second driving current. An active layer of the first light-emitting element is the same as an active layer of the second light-emitting element.
A content of indium in the active layer of the first light-emitting element and a content of indium in the active layer of the second light-emitting element may be in a range from 30% to 45%.
A current density of the first driving current may be lower than a current density of the second driving current.
A first peak current value of the first driving current may be lower than a second peak current value of the second driving current.
A current density of the first driving current may be the same regardless of a gray level of the first light-emitting element, and a current density of the second driving current may be the same regardless of a gray level of the second light-emitting element.
An application period of the first driving current may be adjusted according to the gray level of the first light-emitting element, and an application period of the second driving current may be adjusted according to the gray level of the second light-emitting element.
The application period of the first driving current when the first light-emitting element is to emit light with a peak white gray level may be longer than the application period of the second driving current when the second light-emitting element is to emit light with a peak white gray level.
During one frame period, the application period of the first driving current may be repeated a plurality of times, and the application period of the second driving current may be repeated a plurality of times.
During the one frame period, a sum of the application periods of the first driving current may be longer than a sum of the application periods of the second driving current.
The plurality of light-emitting elements may further include a third light-emitting element that is configured to emit third light according to a third driving current, and an active layer of the third light-emitting element may be different from the active layer of the first light-emitting element and the active layer of the second light-emitting element.
A content of indium in the active layer of the third light-emitting element may be smaller than a content of indium in the active layer of the first light-emitting element and a content of indium in the active layer of the second light-emitting element.
A current density of the third driving current may be adjusted according to a gray level of the third light-emitting element.
According to one or more embodiments of the present disclosure, there is provided a display device including a substrate, a plurality of pixel electrodes on the substrate and spaced apart from each other, a plurality of light-emitting elements respectively on the plurality of pixel electrodes, and a common electrode layer on the plurality of light-emitting elements and to which a common voltage is applied. The plurality of light-emitting elements include a first light-emitting element that is configured to emit first light according to a first driving current, a second light-emitting element that is configured to emit second light according to a second driving current, and a third light-emitting element that is configured to emit third light according to a third driving current. A current density of the first driving current is the same regardless of a gray level of the first light-emitting element, and a current density of the second driving current is the same regardless of a gray level of the second light-emitting element. A current density of the third driving current is adjusted according to a gray level of the third light-emitting element.
The current density of the first driving current may be lower than the current density of the second driving current.
An active layer of the first light-emitting element may be the same as an active layer of the second light-emitting element.
A content of indium in an active layer of the third light-emitting element may be smaller than a content of indium in the active layer of the first light-emitting element and a content of indium in the active layer of the second light-emitting element.
According to one or more embodiments of the present disclosure, there is provided a method of manufacturing a display device, the method including forming a common electrode layer on a substrate, forming a hard mask on the common electrode layer, forming a plurality of first openings exposing the common electrode layer by etching the hard mask, forming first light-emitting elements in some first openings of the plurality of first openings, respectively, and forming second light-emitting elements in remaining first openings of the plurality of first openings, respectively, forming a mask pattern covering the first light-emitting elements and the second light-emitting elements, forming a plurality of second openings exposing the common electrode layer by etching the hard mask, and forming third light-emitting elements in the plurality of second openings, respectively.
A content of indium in an active layer of the third light-emitting element may be smaller than a content of indium in an active layer of the first light-emitting element and a content of indium in an active layer of the second light-emitting element.
A content of indium in the active layer of the first light-emitting element and a content of indium in the active layer of the second light-emitting element may be in a range from 30% to 45%.
The method may further include removing the hard mask and the mask pattern, forming first connection electrodes on the first light-emitting elements, the second light-emitting elements, and the third light-emitting elements, respectively, and forming second connection electrodes on pixel electrodes of a semiconductor circuit board, respectively, and bonding the first connection electrodes and the second connection electrodes.
According to the aforementioned and other embodiments of the present disclosure, each of a plurality of pixels includes a first light-emitting element configured to emit first light, a second light-emitting element configured to emit second light, and a third light-emitting element configured to emit third light, and thus various colors can be displayed without a wavelength conversion layer.
According to the aforementioned and other embodiments of the present disclosure, even though a first light-emitting layer of a first light-emitting element and a first light-emitting layer of a second light-emitting element are formed of the same material, the first light-emitting element can emit first light and the second light-emitting element can emit second light by making the current density of a second driving current applied to the second light-emitting element higher than the current density of a first driving current applied to the first light-emitting element.
According to the aforementioned and other embodiments of the present disclosure, first light-emitting elements, second light-emitting elements, and fourth light-emitting elements may be simultaneously (or concurrently) formed of the same material, so that a manufacturing process can be simplified and manufacturing cost can be reduced as compared with a case in which the first light-emitting elements, the second light-emitting elements, and the fourth light-emitting elements are separately formed.
The above and other embodiments and features of the present disclosure will become more apparent by describing embodiments thereof with reference to the attached drawings, in which:
Aspects and features of some embodiments of the present disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of embodiments and the accompanying drawings.
Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of embodiments of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of embodiments of the present disclosure might not be described.
Unless otherwise noted, like reference numerals, characters, or combinations thereof denote like elements throughout the attached drawings and the written description, and thus, redundant descriptions thereof will not be repeated. Further, parts not related to the description of some embodiments might not be shown to make the description clear.
In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. Additionally, the use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified.
Various embodiments are described herein with reference to sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Further, specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept as well as aspects and features of embodiments of the present disclosure. Thus, embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing.
For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. Additionally, as those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.
In the detailed description, for the purposes of explanation, numerous specific details are set forth to provide a thorough understanding of various embodiments. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments.
Spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “on” a second part, this indicates that the first part is arranged at an upper side or a lower side of the second part without the limitation to the upper side thereof on the basis of the gravity direction.
Further, in this specification, the phrase “on a plane,” or “in a plan view,” means viewing a target portion from the top, and the phrase “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side.
It will be understood that when an element, layer, region, or component is referred to as being “formed on,” “on,” “connected to,” or “coupled to” another element, layer, region, or component, it can be directly formed on, on, connected to, or coupled to the other element, layer, region, or component, or indirectly formed on, on, connected to, or coupled to the other element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. For example, when a layer, region, or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region, or component, it can be directly electrically connected or coupled to the other layer, region, and/or component or intervening layers, regions, or components may be present. However, “directly connected/directly coupled” refers to one component directly connecting or coupling another component without an intermediate component there between. Other expressions describing relationships between components such as “between,” “immediately between” or “adjacent to” and “directly adjacent to” may be construed similarly. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.
For the purposes of this disclosure, expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, and Z,” “at least one of X, Y, or Z,” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, the expressions such as “at least one of A and B” and “at least one of A or B,” may include A, B, or A and B. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. For example, the expression such as “A and/or B” may include A, B, or A and B.
It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure.
In the examples, the x-axis, the y-axis, and/or the z-axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be normal or perpendicular (e.g., substantially perpendicular) to one another, or may represent different directions that are not perpendicular to one another. The same applies for first, second, and/or third directions.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. “About” or “approximately,” as used herein, is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.”
When one or more embodiments may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.
Also, any numerical range disclosed and/or recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, For example, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range subsumed within the ranges expressly recited herein. All such ranges are intended to be inherently described in this specification such that amending to expressly recite any such subranges would comply with the requirements of 35 U.S.C. § 112(a) and 35 U.S.C. § 132(a).
The electronic or electric devices and/or any other relevant devices or components according to one or more embodiments of the present disclosure described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate.
Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning For example consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.
In
In addition, in
In addition, in
Referring to
The display panel 100 may have a quadrangular planar shape having long sides in the first direction DR1 and short sides in the second direction DR2. However, the planar shape of the display panel 100 is not limited thereto, and may have a polygonal shape other than the quadrangular shape, a circular shape, an elliptical shape, or an atypical planar shape.
The display region DA may be a region in which an image is displayed, and the non-display region NDA may be a region in which an image is not displayed. A planar shape of the display region DA may follow a planar shape of the display panel 100. In
The display region DA of the display panel 100 may include a plurality of pixels PX. The pixel PX may include a plurality of light-emitting elements, and may be defined as a minimum light-emitting unit capable of displaying white light by combining light emitted by the plurality of light-emitting elements.
Each of the plurality of pixels PX may include first to fourth light-emitting elements LE1, LE2, LE3, and LE4 that emit light.
The first light-emitting element LE1 may emit a first light. The first light may be light of a red wavelength band. For example, a main peak wavelength (R-peak) of the first light may be positioned at approximately 600 nm to 750 nm, but the embodiment of the present specification is not limited thereto.
The second light-emitting element LE2 and the fourth light-emitting element LE4 may emit a second light. The second light may be light of a green wavelength band. For example, a main peak wavelength (G-peak) of the second light may be positioned at approximately 480 nm to 560 nm, but the embodiment of the present specification is not limited thereto.
The third light-emitting element LE3 may emit a third light. The third light may be light of a blue wavelength band. For example, a main peak wavelength (B-peak) of the third light may be positioned at approximately 370 nm to 460 nm, but the embodiment of the present specification is not limited thereto.
In the display region DA, the first light-emitting elements LE1 and the third light-emitting elements LE3 may be alternately provided with each other in the first direction DR1 and may be repeatedly provided in the second direction DR2. In the display region DA, the second light-emitting elements LE2 and the fourth light-emitting elements LE4 may be repeatedly provided in the first direction DR1 and may be alternately provided with each other in the second direction DR2.
In the display region DA, the first light-emitting elements LE1, the second light-emitting elements LE2, the third light-emitting elements LE3, and the fourth light-emitting elements LE4 may be alternately provided in a first diagonal direction DD1 and a second diagonal direction DD2. In the display region DA, common connection portions CCT may be alternately provided in the first diagonal direction DD1 and the second diagonal direction DD2. The first diagonal direction DD1 may be a diagonal direction between the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 may be a direction crossing (e.g., perpendicular to) the first diagonal direction DD1.
In each of the plurality of pixels PX, the first light-emitting element LE1 and the third light-emitting element LE3 may be arranged with each other in the first direction DR1, and the second light-emitting element LE2 and the fourth light-emitting element LE4 may be arranged with each other in the second direction DR2. In each of the plurality of pixels PX, the first light-emitting element LE1 and the second light-emitting element LE2 may be arranged with each other in the first diagonal direction DD1, the second light-emitting element LE2 and the third light-emitting element LE3 may be arranged with each other in the second diagonal direction DD2, and the third light-emitting element LE3 and the fourth light-emitting element LE4 may be arranged with each other in the first diagonal direction DD1.
The fourth light-emitting element LE4 may be substantially the same as the second light-emitting element LE2. For example, the fourth light-emitting element LE4 may emit the second light, and may have the same structure as the second light-emitting element LE2. The first light may be light of a red wavelength band, the second light may be light of a green wavelength band, the third light may be light of a blue wavelength band, and the fourth light may be light of a green wavelength band.
As shown in
As shown in
In one or more embodiments, the first light-emitting element LE1 is to emit the first light, the second light-emitting element LE2 and the fourth light-emitting element LE4 are to emit the second light, and the third light-emitting element LE3 is to emit the third light, but the embodiment of the present specification is not limited thereto. For example, the first light-emitting element LE1 may emit the first light, the second light-emitting element LE2 and the fourth light-emitting element LE4 may emit the third light, and the third light-emitting element LE3 may emit the second light. In one or more other embodiments, the first light-emitting element LE1 may emit the second light, the second light-emitting element LE2 and the fourth light-emitting element LE4 may emit the first light, and the third light-emitting element LE3 may emit the third light. In one or more other embodiments, the first light-emitting element LE1 may emit the first light, the second light-emitting element LE2 may emit the second light, the third light-emitting element LE3 may emit the third light, and the fourth light-emitting element LE4 may emit the fourth light. The fourth light may be light of a yellow wavelength band. For example, a main peak wavelength of the fourth light may be positioned at approximately 550 nm to 600 nm, but the embodiment of the present specification is not limited thereto.
In one or more embodiments, the first light-emitting element LE1, the second light-emitting element LE2, the third light-emitting element LE3, and the fourth light-emitting element LE4 may have a circular planar shape, but the embodiment of the present specification is not limited thereto. For example, the first light-emitting element LE1, the second light-emitting element LE2, the third light-emitting element LE3, and the fourth light-emitting element LE4 may have polygonal shapes such as a triangle shape, a quadrangular shape, a pentagonal shape, a hexagonal shape, and/or an octagonal shape, an elliptical shape, and/or an atypical shape.
The non-display region NDA may include a first common voltage supply region CVA1, a second common voltage supply region CVA2, a first pad portion PDA1, a second pad portion PDA2, and a peripheral region PHA.
The first common voltage supply region CVA1 may be provided between the first pad region PDA1 and the display region DA. The second common voltage supply region CVA2 may be provided between the second pad region PDA2 and the display region DA. Each of the first common voltage supply region CVA1 and the second common voltage supply region CVA2 may include a plurality of common electrode connection portions CVS connected (e.g., electrically coupled) to a common electrode layer (e.g., CEL in
The plurality of common electrode connection portions CVS of the first common voltage supply region CVA1 may be electrically connected to any one of first pads of the first pad region PDA1. For example, the plurality of common electrode connection portions CVS of the first common voltage supply region CVA1 may receive the common voltage from any one of the first pads of the first pad region PDA1.
The plurality of common electrode connection portions CVS of the second common voltage supply region CVA2 may be electrically connected to any one of second pads of the second pad region PDA2. For example, the plurality of common electrode connection portions CVS of the second common voltage supply region CVA2 may receive the common voltage from any one of the second pads of the second pad region PDA2.
The first pad region PDA1 may be provided at an upper side of the display panel 100. The first pad region PDA1 may include the first pads connected to an external circuit board.
The second pad region PDA2 may be provided at a lower side of the display panel 100. The second pad region PDA2 may include the second pads to be connected to the external circuit board. In some embodiments, the second pad region PDA2 may be omitted.
The peripheral region PHA may be a region in the non-display region NDA excluding the first common voltage supply region CVA1, the second common voltage supply region CVA2, the first pad portion PDA1, and the second pad portion PDA2. The peripheral region PHA may be provided to surround the first common voltage supply region CVA1, the second common voltage supply region CVA2, the first pad portion PDA1, and the second pad portion PDA2 as well as the display region DA.
Referring to
The first light-emitting elements LE1 may be arranged with each other in the second direction DR2. The second light-emitting elements LE2 may be arranged with each other in the second direction DR2. The third light-emitting elements LE3 may be arranged with each other in the second direction DR2.
Although it is exemplified that each of the plurality of pixels PX includes four light-emitting elements LE1, LE2, LE3 and LE4 in
Referring to
The semiconductor circuit board 101 may include a first substrate 110, a plurality of pixel circuit units PXC, pixel electrodes AE, a common electrode connection portion CVS, and a first pad PD1.
The first substrate 110 may be a silicon wafer substrate. The first substrate 110 may be formed of single crystal silicon.
Each of the plurality of pixel circuit units PXC may be provided on the first substrate 110. Each of the plurality of pixel circuit units PXC may include a complementary metal-oxide semiconductor (CMOS) circuit formed using a suitable semiconductor process. Each of the plurality of pixel circuit units PXC may include at least one transistor formed by a suitable semiconductor process. In some embodiments, each of the plurality of pixel circuit units PXC may further include at least one capacitor formed by a suitable semiconductor process.
The plurality of pixel circuit units PXC may be provided in the display region DA. Each of the pixel circuit units PXC provided in the display region DA among the plurality of pixel circuit units PXC may be electrically connected to the pixel electrode AE corresponding thereto. For example, the plurality of pixel circuit units PXC and the plurality of pixel electrodes AE may be connected in a one-to-one correspondence. Each of the plurality of pixel circuit units PXC may apply a pixel voltage to the pixel electrode AE.
The plurality of pixel electrodes AE may be provided in the display region DA. Each of the plurality of pixel electrodes AE may be provided on the pixel circuit unit PXC corresponding thereto. Each of the pixel electrodes AE may be an exposed electrode integrally formed with the pixel circuit unit PXC and exposed from the pixel circuit unit PXC (e.g., from the interface between the pixel electrode AE and the pixel circuit unit PXC). For example, each of the pixel electrodes AE may protrude from an upper surface of the pixel circuit unit PXC. Each of the pixel electrodes AE may receive the pixel voltage from the pixel circuit unit PXC. The pixel electrodes AE may include a metal material such as aluminum (Al).
The plurality of common electrode connection portions CVS may be provided in common electrode regions CPA1 and CPA2 of the non-display region NDA. Each of the plurality of common electrode connection portions CVS may be provided on the pixel circuit unit PXC corresponding thereto. The common electrode connection portion CVS may be an exposed electrode formed integrally with the pixel circuit unit PXC and exposed from the pixel circuit unit PXC (e.g., from the interface between the common electrode connection portion CVS and the pixel circuit unit PXC). For example, each of the common electrode connection portions CVS may protrude from an upper surface of the pixel circuit unit PXC. The common electrode connection portion CVS may include a metal material such as aluminum (Al).
A plurality of first pads PD1 may be provided in the first pad region PDA1 of the non-display region NDA. Each of the plurality of first pads PD1 may be connected to a circuit pad CPD1 of a circuit board 700 through a conductive connection member such as a wire WR. For example, the first pad PD1 and the circuit pad CPD1 of the circuit board 700 may be electrically connected to each other through the wire WR.
In one or more embodiments, the semiconductor circuit board 101 and the circuit board 700 may be provided on a separate lower substrate. The semiconductor circuit board 101 and the circuit board 700 may be attached to an upper surface of the lower substrate using an adhesive member such as a pressure sensitive adhesive.
The circuit board 700 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), a flexible printed circuit (FPC), and/or a flexible film such as a chip on film (COF).
The light-emitting element layer 200 may include light-emitting elements LE1, LE2, LE3, and LE4, a common electrode layer CEL, and connection electrodes CNE1 and CNE2.
Each of the light-emitting elements LE1, LE2, LE3, and LE4 may be provided on the pixel electrode AE corresponding thereto. Each of the light-emitting elements LE1, LE2, LE3, and LE4 may extend in the third direction DR3 (e.g., a thickness direction of the first substrate 110). A length of each of the light-emitting elements LE1, LE2, LE3, and LE4 in the third direction DR3 may be greater than a length in a horizontal direction. The length in the horizontal direction may be a length in the first direction DR1 or the second direction DR2. As an example, a length of each of the light-emitting elements LE1, LE2, LE3, and LE4 in the third direction DR3 may be about 1 μm to 5 μm. Each of the light-emitting elements LE1, LE2, LE3, and LE4 may have a cylindrical shape, a disk shape, and/or a rod shape with a width greater than a height (e.g., a length is larger than a thickness). However, the embodiment is not limited thereto, and each of the light-emitting elements LE1, LE2, LE3, and LE4 may have a shape of a rod, a wire, a tube, etc., a polygonal prism shape such as a cubic shape, a rectangular parallelepiped shape, and/or a hexagonal prism shape, and/or various suitable shapes such as a shape extending in one direction and having an outer surface partially inclined.
According to one or more embodiments, each of the light-emitting elements LE1, LE2, LE3, and LE4 may include a first semiconductor layer PSEM, an electron blocking layer EBL, an active layer MQW1 or MQW2, a superlattice layer SLT, and a second semiconductor layer NSEM. The first semiconductor layer PSEM, the electron blocking layer EBL, the active layers MQW1/MQW2, the superlattice layer SLT, and the second semiconductor layer NSEM may be sequentially stacked in the third direction DR3.
The first semiconductor layer PSEM may be a p-type semiconductor and may include a semiconductor material having a chemical formula of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer PSEM may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, or InN doped with a p-type dopant. The first semiconductor layer PSEM may be doped with a p-type dopant, and the p-type dopant may include Mg, Zn, Ca, Ba, and/or the like. For example, the first semiconductor layer PSEM may be p-GaN doped with Mg that is the p-type dopant. The first semiconductor layer PSEM may have a thickness in a range from about 30 nm to about 200 nm.
The electron blocking layer EBL may be provided on the first semiconductor layer PSEM. The electron blocking layer EBL may prevent or reduce the injection of electrons flowing into the active layers MQW1/MQW2 into another layer without recombination with holes in the active layers MQW1/MQW2. For example, the electron blocking layer EBL may be p-AlGaN doped with Mg that is the p-type dopant. A thickness of the electron blocking layer EBL may be in a range from about 10 nm to about 50 nm, but the embodiment is not limited thereto. In some embodiments, the electron blocking layer EBL may not be provided.
The active layers MQW1/MQW2 may be provided on the electron blocking layer EBL. The active layers MQW1/MQW2 may emit light by recombination of electrons and holes according to an emission signal applied through the first semiconductor layer PSEM and the second semiconductor layer NSEM. The active layers MQW1/MQW2 may include a material having a single or multiple quantum well structure. When the active layers MQW1/MQW2 include a material having a multiple quantum well structure, the active layers MQW1/MQW2 may have a quantum well structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN and/or AlGaN, but the embodiment is not limited thereto. For example, the active layers MQW1/MQW2 may have a structure in which a semiconductor material having large band gap energy and a semiconductor material having small band gap energy are alternately stacked, and may include other Group Ill to V semiconductor materials depending on the wavelength band of the emitted light.
The superlattice layer SLT is provided on the active layers MQW1/MQW2. The superlattice layer SLT may relieve stress due to a difference in lattice constant between the second semiconductor layer NSEM and the active layers MQW1/MQW2. For example, the superlattice layer SLT may be formed of InGaN and/or GaN. A thickness of the superlattice layer SLT may be approximately 50 nm to 200 nm. However, the superlattice layer SLT may not be provided.
The second semiconductor layer NSEM may be provided on the superlattice layer SLT. The second semiconductor layer NSEM may be an n-type semiconductor. The second semiconductor layer NSEM may include a semiconductor material having a chemical formula of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer NSEM may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, or InN doped with an n-type dopant. The second semiconductor layer NSEM may be doped with an n-type dopant, and the n-type dopant may include Si, Ge, Sn, and/or the like. For example, the second semiconductor layer NSEM may be n-GaN doped with Si that is the n-type dopant. A thickness of the second semiconductor layer NSEM may be in a range from about 500 nm to about 1 μm, but the embodiment is not limited thereto.
According to one or more embodiments, each of the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4 may include a first active layer MQW1, and the third light-emitting elements LE3 may include a second active layer MQW2. When the active layers MQW1/MQW2 are formed of InGaN, a color of light emitted from the active layers MQW1/MQW2 may be changed depending on the content of indium (In). For example, as the content of indium (In) increases, a wavelength band of light emitted from the active layer may move to the red wavelength band, and as the content of indium (In) decreases, the wavelength band of light emitted from the active layer may move to the blue wavelength band. The content of indium (In) in the first active layer MQW1 may be greater than the content of indium (In) in the second active layer MQW2. For example, the content of indium (In) in the first active layer MQW1 may be approximately 30% to 45%, and the content of indium (In) in the second active layer MQW2 may be approximately 10% to 20%. In this case, the first active layer MQW1 may emit the first light or the second light depending on a current density, and the second active layer MQW2 may emit the third light.
It is exemplified in
The common electrode layer CEL may be provided on the light-emitting elements LE1, LE2, LE3, and LE4. The common electrode layer CEL may be connected to the second semiconductor layer NSEM of each of the light-emitting elements LE1, LE2, LE3, and LE4 as one common layer.
The common electrode layer CEL may be an n-type semiconductor including the same material as the second semiconductor layer NSEM. The common electrode layer CEL may include a semiconductor material having a chemical formula of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the common electrode layer CEL may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, or InN doped with an n-type dopant. The common electrode layer CEL may be doped with an n-type dopant, and the n-type dopant may include Si, Ge, Sn, and/or the like. For example, the common electrode layer CEL may be n-GaN doped with Si that is the n-type dopant.
As described above, the common electrode layer CEL may be formed of the same material as the second semiconductor layer NSEM and is integrated with the second semiconductor layer NSEM (see e.g.,
Each of the first connection electrodes CNE1 may be provided between the light-emitting elements LE1, LE2, LE3, and LE4 corresponding thereto and the pixel electrodes AE in the display region DA. Each of the first connection electrodes CNE1 may be in contact with one surface of the first semiconductor layer PSEM of the light-emitting elements LE1, LE2, LE3, and LE4 corresponding thereto. Each of the first connection electrodes CNE1 may be in contact with one surface of the pixel electrode AE corresponding thereto. Each of the first connection electrodes CNE1 may transmit the pixel voltage applied to the pixel electrodes AE to the light-emitting elements LE1, LE2, LE3, and LE4. A width of the first connection electrode CNE1 may be smaller than the width of each of the light-emitting elements LE1, LE2, LE3, and LE4, but the embodiment is not limited thereto.
Each of the first connection electrodes CNE1 may serve as a bonding metal for bonding the pixel electrode AE and the corresponding one of the light-emitting elements LE1, LE2, LE3, and LE4 to each other during a manufacturing process. Each of the first connection electrodes CNE1 may include a material that may be electrically connected to the pixel electrode AE and the corresponding one of the light-emitting elements LE1, LE2, LE3, and LE4. For example, the first connection electrode CNE1 may include at least one of gold (Au), copper (Cu), aluminum (Al), or tin (Sn), and/or may include a transparent conductive oxide such as indium tin oxide (ITO) and/or indium zinc oxide (IZO). In one or more embodiments, the first connection electrode CNE1 may include a first layer including any one of gold (Au), copper (Cu), aluminum (Al), or tin (Sn), and a second layer including another one of gold (Au), copper (Cu), aluminum (Al), or tin (Sn).
A second connection electrode CNE2 may be connected to the common electrode connection portion CVS corresponding thereto. The second connection electrode CNE2 may be provided on the common electrode connection portion CVS. The second connection electrode CNE2 may extend in the third direction DR3 and may be connected to the common electrode layer CEL. A height of the second connection electrode CNE2 may be substantially equal to a combined height of the light emitting element of the light-emitting elements LE1, LE2, LE3, and LE4 and the corresponding first connection electrode CNE1.
The second connection electrode CNE2 may include a material that may be electrically connected to the common electrode connection portion CVS. The second connection electrode CNE2 may be formed of the same material as the first connection electrode CNE1. For example, the second connection electrode CNE2 may include at least one of gold (Au), copper (Cu), aluminum (Al), or tin (Sn). In one or more embodiments, the second connection electrode CNE2 may include a first layer including any one of gold (Au), copper (Cu), aluminum (Al), or tin (Sn), and a second layer including another one of gold (Au), copper (Cu), aluminum (Al), or tin (Sn).
The second semiconductor layers SEM2 of the light-emitting elements LE1, LE2, LE3, and LE4 may be electrically connected to each other through the common electrode layer CEL. For example, the common electrode layer CEL may include the same material as the second semiconductor layer SEM2, and the second semiconductor layer SEM2 of each of the light-emitting elements LE1, LE2, LE3, and LE4 may be formed integrally with the common electrode layer CEL. For example, the second semiconductor layer SEM2 of each of the light-emitting elements LE1, LE2, LE3, and LE4 may protrude (e.g., downward) from the common electrode layer CEL.
The second semiconductor layers SEM2 may be spaced apart from each other.
The common electrode layer CEL may be electrically connected to the common electrode connection portion CVS of the semiconductor circuit board 101 through the second connection electrode CNE2 provided in the common electrode regions CPA1 and CPA2. Accordingly, the common electrode layer CEL may receive the common voltage through the common electrode connection portion CVS of the semiconductor circuit board 101.
As shown in
Referring to
In this case, light emitted from the first light-emitting element LE1 and the second light-emitting element LE2 may be shifted from red to blue depending on a current density. For example, a band gap between the first light-emitting layer MQW1 of the first light-emitting element LE1 and the first light-emitting layer MQW1 of the second light-emitting element LE2 may be changed from a rectangular shape as shown in
As described above, even though the first light-emitting layer MQW1 of the first light-emitting element LE1 and the first light-emitting layer MQW1 of the second light-emitting element LE2 are formed of the same material, for example, the first light-emitting layer MQW1 of the first light-emitting element LE1 and the first light-emitting layer MQW1 of the second light-emitting element LE2 are formed of InGaN having an indium (In) content of 30% to 45%, it is possible to control the emission of the light having a long wavelength and the light having a short wavelength by adjusting the current density of the driving current applied to the first light-emitting layer MQW1.
Referring to
Because the current density of the second driving current Ids2 is greater than the current density of the first driving current Ids1, a second peak current value Ipeak2 of the second driving current Ids2 may be higher than a first peak current value Ipeak1 of the first driving current Ids1.
The gray level of the first light-emitting element LE1 may be adjusted depending on a period EP1 in which the first driving current Ids1 is applied to the first light-emitting element LE1. For example, in the first light-emitting element LE1, as the application period EP1 of the first driving current Ids1 increases, it is possible to express gray level close to the peak white gray level, and as the application period EP1 of the first driving current Ids1 decreases, it is possible to express gray level close to the peak black gray level.
The gray level of the second light-emitting element LE2 may be adjusted depending on a period EP2 in which the second driving current Ids2 is applied to the second light-emitting element LE2. For example, in the second light-emitting element LE2, as the application period EP2 of the second driving current Ids2 increases, it is possible to express gray level close to the peak white gray level, and as the application period EP2 of the second driving current Ids2 decreases, it is possible to express gray level close to the peak black gray level.
Because the current density of the first driving current Ids1 is lower than the current density of the second driving current Ids2, the application period EP1 of the first driving current Ids1 applied to the first light-emitting element LE1 expressing the peak white gray level may be longer than the application period EP2 of the second driving current Ids2 applied to the second light-emitting element LE2 expressing the peak white gray level. For example, when the first light-emitting element LE1 and the second light-emitting element LE2 express the same gray level, the application period EP1 of the first driving current Ids1 may be longer than the application period EP2 of the second driving current Ids2.
Because the fourth light-emitting element LE4 emits the second light substantially the same as that of the second light-emitting element LE2, the fourth driving current applied to the fourth light-emitting element LE4 may be substantially equal to the second driving current Ids2 described with reference to
In one or more embodiments, the third light-emitting element LE3 may emit light depending on the third driving current. The gray level expression of the third light-emitting element LE3 may be similar to that of the first light-emitting element LE1 and the second light-emitting element LE2. For example, a current density of the third driving current may be the same regardless of the gray level of the third light-emitting element LE3. In this case, the gray level of the third light-emitting element LE3 may be adjusted depending on a period in which the third driving current is applied to the third light-emitting element LE3. For example, in the third light-emitting element LE3, as the application period of the third driving current increases, it is possible to express gray level close to the peak white gray level, and as the application period of the third driving current decreases, it is possible to express gray level close to the peak black gray level.
In one or more embodiments, the gray level of the third light-emitting element LE3 may be adjusted depending on the current density of the third driving current. For example, as the current density of the third driving current increases, the gray level of the third light-emitting element LE3 expresses gray level close to the peak white gray level, and as the current density of the third driving current decreases, the gray level of the third light-emitting element LE3 expresses gray level close to the peak black gray level.
As described above, even though the first light-emitting layer MQW1 of the first light-emitting element LE1 and the first light-emitting layer MQW1 of the second light-emitting element LE2 are formed of the same material, the first light-emitting element LE1 may emit the first light and the second light-emitting element LE2 may emit the second light by making the current density of the second driving current Ids2 applied to the second light-emitting element LE2 higher than the current density of the first driving current Ids1 applied to the first light-emitting element LE1.
In some embodiments, in order for the first light-emitting element LE1 to emit the first light of the same wavelength band regardless of the gray level, the current density of the first driving current Ids1 may be controlled to be the same regardless of the gray level, and the gray level of the first light-emitting element LE1 may be adjusted depending on the application period EP1 of the first driving current Ids1. order for the second light-emitting element LE2 to emit the second light of the same wavelength band regardless of the gray level, the current density of the second driving current Ids2 may be controlled to be the same regardless of the gray level, and the gray level of the second light-emitting element LE2 may be adjusted depending on the application period EP2 of the second driving current Ids2.
The embodiment of
Referring to
The second driving current Ids2 may be applied to the second light-emitting element LE2 P times during one frame period. For example, the one frame period may include an application period EP2′ of the second driving current Ids2 P times. The application period EP2′ of the second driving current Ids2 P times may be equal to each other.
The gray level of the first light-emitting element LE1 may be adjusted depending on the application period EP1′ of the first driving current Ids1. For example, in the first light-emitting element LE1, as the application period EP1′ of the first driving current Ids1 increases, it is possible to express gray level close to the peak white gray level, and as the application period EP1′ of the first driving current Ids1 decreases, it is possible to express gray level close to the peak black gray level.
The gray level of the second light-emitting element LE2 may be adjusted depending on the application period EP2′ of the second driving current Ids2. For example, in the second light-emitting element LE2, as the application period EP2′ of the second driving current Ids2 increases, it is possible to express gray level close to the peak white gray level, and as the application period EP2′ of the second driving current Ids2 decreases, it is possible to express gray level close to the peak black gray level.
Because the current density of the first driving current Ids1 is lower than the current density of the second driving current Ids2, when the first light-emitting element LE1 and the second light-emitting element LE2 express the same gray level, the application period EP1′ of the first driving current Ids1 may be longer than the application period EP2′ of the second driving current Ids2. In addition, because the first driving current Ids1 is applied to the first light-emitting element LE1 P times during one frame period and the second driving current Ids2 is applied to the second light-emitting element LE2 P times during one frame period, the sum of the application periods EP1′ of the first driving current Ids1 may be longer than the sum of the application periods EP2′ of the second driving current Ids2 during the one frame period.
Because the fourth light-emitting element LE4 emits the second light substantially the same as that of the second light-emitting element LE2, the fourth driving current applied to the fourth light-emitting element LE4 may be substantially equal to the second driving current Ids2 described with reference to
In addition, because the third driving current may also be similar to the first driving current Ids1 and the second driving current Ids2 described with reference to
The embodiment of
Referring to
Because the area of the first light-emitting element LE1 is greater than the area of the second light-emitting element LE2, the area of the third light-emitting element LE3, and the area of the fourth light-emitting element LE4, a distance between the first light-emitting element LE1 and the second light-emitting element LE2 adjacent to each other and a distance between the first light-emitting element LE1 and the fourth light-emitting element LE4 adjacent to each other may be smaller than a distance between the second light-emitting element LE2 and the third light-emitting elements LE3 adjacent to each other and a distance between the third light-emitting elements LE3 and the fourth light-emitting element LE4 adjacent to each other. The distance between the first light-emitting element LE1 and the second light-emitting element LE2 adjacent to each other and the distance between the first light-emitting element LE1 and the fourth light-emitting element LE4 adjacent to each other may be substantially the same. The distance between the second light-emitting element LE2 and the third light-emitting elements LE3 adjacent to each other and the distance between the third light-emitting elements LE3 and the fourth light-emitting element LE4 adjacent to each other may be substantially the same.
Referring to
Hereinafter, the method of manufacturing a display device according to one or more embodiments will be described in more detail with reference to
First, as shown in
The second substrate 210 may be a sapphire substrate (Al2O3) and/or a silicon wafer including silicon. However, the second substrate 210 is not limited thereto, and the second substrate 210 may be a semiconductor substrate such as a GaAs substrate. Hereinafter, a case in which the second substrate 210 is a sapphire substrate will be described as an example.
The undoped semiconductor layer USEM may include an undoped semiconductor, and may be a material that is not doped with an n-type or a p-type dopant. For example, the undoped semiconductor layer USEM may include at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, or InN, but the embodiment is not limited thereto. It is exemplified in
The common electrode layer CEL may include an n-type semiconductor. For example, the common electrode layer CEL may include one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, or InN doped with an n-type dopant.
The undoped semiconductor layer USEM and the common electrode layer CEL may be formed by an epitaxial growth method. An epitaxial growth process may include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), and/or the like. As an example, the epitaxial growth process may be performed by a metal-organic chemical vapor deposition (MOCVD) method, but the embodiment is not limited thereto.
A precursor material for forming a plurality of semiconductor material layers is not particularly limited and may include any suitable target material. As an example, the precursor material may be a metal precursor including an alkyl group such as a methyl group and/or an ethyl group. For example, the precursor material may be a compound such as trimethyl gallium (Ga(CH3)3), trimethyl aluminum (Al(CH3)3), and/or triethyl phosphate ((C2H5)3PO4), but the embodiment is not limited thereto.
Second, as shown in
The hard mask HM may be entirely on the common electrode layer CEL. The hard mask HM may include an insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and/or the like. The hard mask HM may function as a mask in a process for forming the light-emitting elements LE1, LE2, LE3, and LE4.
Third, as shown in
In one or more embodiments, a separate mask is provided on the hard mask HM except for a region where the plurality of first openings OP1 are formed, and the hard mask HM is etched by wet etching or dry etching, thereby forming the plurality of first openings OP1.
The plurality of first openings OP1 may be formed to be spaced apart from each other. The spacing and width of the plurality of first openings OP1 may be set in consideration of the arrangement and width of the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4.
Fourth, as shown in
The process of forming the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4 may be performed by an epitaxial growth method. When an upper surface of the common electrode layer CEL is exposed through the plurality of first openings OP1, a semiconductor crystal is grown by injecting the precursor material onto the common electrode layer CEL. A second semiconductor layer NSEM of each of the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4 provided on the common electrode layer CEL includes substantially the same material as the common electrode layer CEL, and may be formed by growing a semiconductor crystal of the common electrode layer CEL. Accordingly, the common electrode layer CEL and the second semiconductor layer NSEM of each of the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4 may be integrated (e.g., may be integrally formed).
Then, a superlattice layer SLT, a first active layer MQW1, an electron blocking layer EBL, and a first semiconductor layer PSEM are sequentially grown to complete the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4, respectively. In operation S140, the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4 having the first active layer MQW1 may be formed.
Fifth, as shown in
The mask pattern MP may be formed of an inorganic film such as a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), and/or a hafnium oxide film (HfOx), but the embodiment of the present specification is not limited thereto. The mask pattern MP may include the same material as the hard mask HM.
The mask pattern MP may be a protective film (e.g., a barrier film) for protecting the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4. The mask pattern MP may be provided to cover each of the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4. In some embodiments, the mask pattern MP may be provided to cover the entire upper surface of the hard mask HM.
Sixth, as shown in
In one or more embodiments, a separate mask is provided on the hard mask HM except for a region where the plurality of second openings OP2 are to be formed, and the hard mask HM is etched by wet etching or dry etching, thereby forming the plurality of second openings OP2.
The plurality of second openings OP2 may be formed to be spaced apart from each other. The spacing and width of the plurality of second openings OP2 may be set in consideration of the arrangement and width of the third light-emitting elements LE3.
Seventh, as shown in
The process of forming the third light-emitting elements LE3 may be performed by an epitaxial growth method. When an upper surface of the common electrode layer CEL is exposed through the plurality of second openings OP2, a semiconductor crystal is grown by injecting a precursor material onto the common electrode layer CEL. The second semiconductor layer NSEM of each of the third light-emitting elements LE3 provided on the common electrode layer CEL includes substantially the same material as the common electrode layer CEL, and may be formed by growing the semiconductor crystal of the common electrode layer CEL. Accordingly, the common electrode layer CEL and the second semiconductor layer NSEM of each of the third light-emitting elements LE3 may be integrated (e.g., may be integrally formed).
Then, a superlattice layer SLT, a second active layer MQW2, an electron blocking layer EBL, and a first semiconductor layer PSEM are sequentially grown to complete the third light-emitting elements LE3. In operation S170, the third light-emitting elements LE3 having the second active layer MQW2 may be formed.
Eighth, as in
The hard mask HM and the mask pattern MP may be etched at once through an etching process. The etching process may be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), and/or the like.
Then, the first sub-connection electrode SCNE1 may be formed on an upper surface of the first semiconductor layer PSEM of each of the light-emitting elements LE1, LE2, LE3, and LE4 through a photolithography process.
The second sub-connection electrode SCNE2 may be formed on the common electrode layer CEL through the photolithography process.
Further, the third sub-connection electrodes SCNE3 may be respectively formed on the pixel electrodes AE and the common electrode connection portions CVS of the semiconductor circuit board 101 through the photolithography process.
The first sub-connection electrodes SCNE1, the second sub-connection electrode SCNE2, and the third sub-connection electrodes SCNE3 may serve as the bonding metal. For example, the first sub-connection electrodes SCNE1, the second sub-connection electrode SCNE2, and the third sub-connection electrodes SCNE3 may include at least one of gold (Au), copper (Cu), aluminum (Al), or tin (Sn), and/or may include a transparent conductive oxide such as indium tin oxide (ITO) and/or indium zinc oxide (IZO).
Ninth, as shown in
The first sub-connection electrodes SCNE1 of the second substrate 210 may be aligned to respectively correspond to the pixel electrodes AE of the semiconductor circuit board 101. Also, the second sub-connection electrode SCNE2 of the second substrate 210 may be aligned to correspond to the common electrode connection portions CVS of the first substrate 110. For example, the first sub-connection electrodes SCNE1 of the second substrate 210 may overlap the pixel electrodes AE of the semiconductor circuit board 101 in the third direction DR3, respectively. The second sub-connection electrode SCNE2 of the second substrate 210 may overlap the common electrode connection portions CVS of the first substrate 110 in the third direction DR3.
Then, the first sub-connection electrodes SCNE1 and the second sub-connection electrode SCNE2 of the second substrate 210 are brought into contact with the third sub-connection electrodes SCNE3 of the semiconductor circuit board 101. Then, the first sub-connection electrodes SCNE1, the second sub-connection electrode SCNE2, and the third sub-connection electrodes SCNE3 are melt-bonded at a set or predetermined temperature. Accordingly, the second substrate 210 may be bonded to the semiconductor circuit board 101.
Tenth, as shown in
The second substrate 210 may be separated from the undoped semiconductor layer USEM by a laser lift-off process. In one or more embodiments, the second substrate 210 may be removed through a polishing process such as a chemical mechanical polishing (CMP) process and/or an etching process.
The undoped semiconductor layer USEM may be removed through a polishing process such as a CMP process, and/or may be removed by wet etching and/or dry etching. When the undoped semiconductor layer USEM is removed, a part of the common electrode layer CEL may be removed.
As described above, the first light-emitting elements LE1, the second light-emitting elements LE2, and the fourth light-emitting elements LE4 are simultaneously (e.g., concurrently) formed of the same material, and the first light-emitting elements LE1 may emit the first light and the second light-emitting elements LE2 and the fourth light-emitting elements LE4 may emit the second light by making the current density of the second driving current Ids2 applied to the second light-emitting elements LE2 and the current density of the fourth driving current Ids4 applied to the fourth light-emitting elements LE4 higher than the current density of the first driving current Ids1 applied to the first light-emitting elements LE1. Accordingly, a manufacturing process may be simplified and manufacturing cost may be reduced as compared with a case in which the first light-emitting elements LE1 emitting the first light, the second light-emitting elements LE2 and the fourth light-emitting elements LE4 emitting the second light, and the third light-emitting elements LE43 emitting the third light are separately formed.
Referring to
The display device accommodating unit 50 may include the display device 10_1 and the reflective member 40. An image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the right eye of a user through the right eye lens 10b. Accordingly, the user may view a virtual reality image displayed on the display device 10_1 through the right eye.
It is exemplified in
Referring to
Referring to
Referring to
However, the aspects and features of embodiments of the present disclosure are not limited to the one set forth herein. The above and other aspects and features of embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the claims, with functional equivalents thereof to be included therein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0135760 | Oct 2021 | KR | national |
This application is a continuation of U.S. patent application Ser. No. 17/855,251, filed Jun. 30, 2022, which claims priority to and the benefit of Korean Patent Application No. 10-2021-0135760 filed on Oct. 13, 2021, in the Korean Intellectual Property Office (KIPO), the entire content of which is incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17855251 | Jun 2022 | US |
| Child | 18611413 | US |
