Patent Application
20120074559
1. Technical Field
The disclosure relates generally to integrated circuit (IC) chips, and more particularly, to an integrated circuit package using through substrate vias to ground a lid to, for example, limit electro-magnetic interference.
2. Background Art
Regulations exist to limit the extent of electro-magnetic interference (EMI) for a given integrated circuit (IC) chip. EMI can be limited in a number of ways. One currently evolving manner of limiting EMI is to provide a grounded lid to an IC chip. When a ground lid is used, a lip of the metal lid is electrically coupled to a ground plane in the package substrate (i.e., laminate) using a ball grid array (BGA) of the package substrate and/or controlled collapse chip connectors (C4) between the package substrate and the IC chip. The metal lid acts to suppress EMI through its grounded connection. However, the effectiveness of the lid is limited because only a small portion of the lid is effectively grounded for the frequency of EMI emissions, i.e., the outer lip. Consequently, the grounding efficacy is not uniform across the lid for all emission frequencies.
A first aspect of the disclosure provides an integrated circuit package, comprising: a package substrate; a metal lid mounted to the package substrate; and a stack of two or more integrated circuit chips electrically connected to each other by through substrate vias, the stack of two or more integrated circuit chips disposed within the metal lid and electrically mounted to the package substrate, wherein an inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias.
A second aspect of the disclosure provides an integrated circuit package, comprising: a package substrate; a metal lid mounted to the package substrate; a stack of two or more integrated circuit chips electrically connected to each other by axially aligned through substrate vias running from a bottom of a lowermost integrated circuit chip of the two or more integrated circuit chips to an upper surface of an uppermost integrated circuit chip of the two or more integrated circuit chips, the stack of two or more integrated circuit chips disposed within the metal lid and electrically mounted to the package substrate; and a conductive thermal interface material (TIM) between the upper surface of the uppermost integrated circuit chip and the metal lid, wherein an inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the conductive TIM and the through substrate vias.
A third aspect of the disclosure provides an integrated circuit package, comprising: a package substrate; a metal lid mounted to the package substrate; and an integrated circuit chip including a plurality of through substrate vias running from a bottom of the integrated circuit chip to an upper surface of the integrated circuit chip, wherein an inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias.
The illustrative aspects of the present disclosure are designed to solve the problems herein described and/or other problems not discussed.
These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which:
It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
As indicated above, the disclosure provides an integrated circuit package including a package substrate, a metal lid mounted to the package substrate, and a stack of two or more integrated circuit chips electrically connected to each other by through substrate vias. The stack of two or more integrated circuit chips is disposed within the metal lid and electrically mounted to the package substrate. An inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias (TSVs). The TSVs provide electromagnetic and radio frequency interference shielding. A conductive thermal interface material may also be used.
Referring to
A metal lid 110 is mounted to package substrate 102. Metal lid 110 may be made of any now known or conventional material typically used for a lid of a chip package, e.g., aluminum, copper, etc., or alloys thereof. Metal lid 110 is mechanically positioned on chips 120 and has a thickness greater than a simple coating, the latter of which could be applied by a chemical process. Metal lid 110 could be removed and/or replaced using mechanical tools, and could not be positioned within a chip 120. Although not shown for clarity, it is understood that metal lid 110 could also include other conventional thermal transfer structures such as a heat sink or a heat spreader (not shown). As illustrated metal lid 110 includes a top 106 and sidewalls 114. As illustrated, metal lid 110 completely surrounds a top and sidewalls of a stack 118 of two or more integrated circuit (IC) chips 120. That is, sidewalls 114 may exist on four sides of metal lid 110 so as to create an open, rectangular box shape (open downwardly as drawn). However, as shown in
A stack 118 of two or more integrated circuit (IC) chips 120 are disposed within metal lid 110 and electrically mounted to package substrate 102. In
In accordance with embodiments of the invention, an inner surface 140 of top 106 of metal lid 110 is electrically connected to ground wires 108 in package substrate 102 by through substrate vias 130. That is, TSVs 130 extend through an upper surface of uppermost chip 120U and are exposed such that they can contact inner surface 140 of top 106 of metal lid 110 (or TIM 142 where used, described elsewhere herein). Use of TSVs 130 to make the connection to metal lid 110 lowers the resistance path between metal lid 110 and chips 120 and package substrate 102. In addition, TSVs 130 provide a set of off-axis antennas to absorb and synchronize additional electromagnetic radiation. A metal lid to chip to package substrate connection allows provision of structures closer to a Faraday cage to isolate IC chips 120 from electromagnetic interference (EMI) and maintain chips 120 from affecting their surroundings with EMI.
Referring to
Referring to
Although IC chip package 100 has been described herein as including a stack 118 of IC chips 120, in an alternative embodiment, shown in
The above-described integrated circuit packages can be distributed by the fabricator as is or may be combined into another multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chips are then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from cell phones, toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
