The present invention relates in general to integrated circuit packaging, and more particularly to a leadless plastic chip carrier with features for improved thermal performance.
According to well known prior art IC (integrated circuit) packaging methodologies, semiconductor dice are singulated and mounted using epoxy or other conventional means onto respective die attach pads of a leadframe strip. Traditional QFP (Quad Flat Pack) packages incorporate inner leads which function as lands for wire bonding the semiconductor die bond pads. These inner leads typically require mold locking features to ensure proper positioning of the leadframe strip during subsequent molding to encapsulate the package. The inner leads terminate in outer leads that are bent down to contact a mother board, thereby limiting the package density of such prior art devices.
In order to overcome these and other disadvantages of the prior art, the Applicants previously developed a Leadless Plastic Chip Carrier (LPCC). According to Applicants' LPCC fabrication methodology, a leadframe strip is provided for supporting up to several hundred devices. Singulated IC dice are placed on the strip die attach pads using conventional die mount and epoxy techniques. After curing of the epoxy, the dice are gold wire bonded to peripheral internal leads. The leadframe strip is then molded in plastic or resin using a modified mold in which the bottom cavity is a flat plate. In the resulting molded package, the die pad and leadframe inner leads are exposed. By exposing the bottom of the die attach pad, mold delamination at the bottom of the die attach pad is inhibited, thereby increasing the moisture sensitivity performance. Also, thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard. By exposing the leadframe inner leads, the requirement for mold locking features is eliminated and no external lead standoff is necessary, thereby increasing device density and reducing package thickness over prior art methodologies. The exposed inner leadframe leads function as solder pads for motherboard assembly such that less gold wire bonding is required as compared to prior art methodologies, thereby improving electrical performance in terms of board level parasitics and enhancing design flexibility over prior art packages (i.e. custom trim tools and form tools are not required). These and several other advantages of Applicants' own prior art LPCC process are detailed in Applicants' U.S. Pat. No. 6,229,200, issued May 8, 2001, the entire contents of which are incorporated herein by reference.
Applicant's LPCC production methodology utilizes saw singulation to isolate the perimeter I/O row as well as multi-row partial lead isolation. Specifically, the leadframe strip is mounted to a wafer saw ring using adhesive tape and saw-singulated using a conventional wafer saw. The singulation is guided by a pattern formed by fiducial marks on the second side (bottom) of the leadframe strip. Also, special mold processing techniques are used to keep the mold from bleeding onto the functional pad area and inhibiting electrical contact. Specifically, the exposed die pad surface is required to be deflashed after molding to remove any molding compound residue and thereby allow the exposed leads and die attach pad to serve as solder pads for attachment to the motherboard.
According to Applicant's own U.S. Pat. No. 6,498,099, issued Dec. 24, 2002, the contents of which are incorporated herein by reference, a localized etch process is provided for the improved manufacture of the LPCC IC package. The leadframe strip is subjected to a partial etch on one or both of the top and bottom sides in order to create a pattern of contact pads and a die attach pad.
Further improvements in IC packages are driven by industry demands for increased electrical performance and decreased size and cost of manufacture. With continued improvements in electrical performance and decreasing package size, improvements in thermal performance are needed. In particular, further improvements in heat dissipation are desirable, particularly in high power applications.
In one aspect of the present invention, there is provided a process for fabricating a leadless plastic chip carrier that includes: providing a leadframe including a plurality of contacts circumscribing a void; fixing a heat sink to the contacts of the leadframe using an intermediate non-electrically conductive adhesive such that the heat sink spans the void; mounting a semiconductor die to the heat sink in the void; wire bonding ones of the contacts to the pads of the semiconductor die; encapsulating the semiconductor die and the wire bonds in a molding material and singulating the leadless plastic chip carrier.
In another aspect of the present invention, there is provided a leadless plastic chip carrier. The leadless plastic chip carrier includes a heat sink. A semiconductor die is fixed to the heat sink using an intermediary electrically non-conductive adhesive. A plurality of contacts are fixed to the heat sink such that the contacts circumscribe the semiconductor die. A plurality of wire bonds connect pads of the semiconductor die to ones of the contacts and a molding material encapsulates the semiconductor die and the wire bonds.
Advantageously, the heat sink provides a direct thermal path from the semiconductor die to the exterior of the package. The use of any thermally conductive but non-electrically conductive adhesive allows heat from the semiconductor die to be transferred from the exposed heat sink or through the adhesive to the contacts which are soldered to the motherboard. In embodiments of the present invention, a cavity is provided in the heat sink and the semiconductor die is mounted in the cavity. This feature allows for shorter wire bond lengths which results in decreased electrical impedance and increased thermal performance.
The integrated circuit package according to embodiments of the present invention is suitable for high power applications in which a motherboard has insufficient heat capacity to dissipate all heat from the semiconductor die. Further, the integrated circuit package is suitable in applications in which insufficient space is available on the motherboard for soldering a die attach pad. The integrated circuit package according to embodiments of the present invention provides for a heat sink that acts as a die attach pad on an opposite side of input/output contact leads. The heat sink (die attach pad) dimension can be standard for a particular package dimension, independent to the semiconductor die size and wire bond requirement, thereby providing a cost effective design that also provides for integration of power and ground signals in the package.
The present invention will be better understood with reference to the drawings and the following description, in which like numeral denote like parts and in which:
Reference is made to
A process for manufacturing the LPCC package 20 will now be described in more detail. Referring to
The copper panel substrate 32 is selectively etched by, for example, spin coating a photo-imageable etch resistant mask on both sides of the copper panel substrate 32, selectively exposing the etch resistant mask using a photo tool, developing the etch resistant mask to expose portions of the copper panel substrate, pressurized spray etching the exposed portions of the copper panel substrate 32 and removing the remainder of the etch resistant mask. After removal of the etch resistant mask, the leadframe strip is electrolytically plated with a suitable metal, such as silver (Ag) or successive layers of nickel (Ni), palladium (Pd) and then gold (Au). The resulting leadframe strip is shown in
As best shown in
Referring now to
Next, the heat sink array is fixed to the leadframe strip using an electrically non-conductive adhesive, as best shown in
A singulated semiconductor die 24 is conventionally mounted via epoxy (or other suitable means) to the heat sink 22, and the epoxy is cured. As shown in
The semiconductor die 24, wire bonds 28 and the interior portions 34 of the contacts 26 are then encapsulated in a molding material 30, as shown in
After encapsulating, the exposed surface of each of the contacts 26 is electrolytically plated with a layer of nickel (Ni).
The individual LPCC package 20 is then singulated by, for example, saw singulation.
Reference is now made to
A process for manufacturing the LPCC package 20 will now be described in more detail. Referring to
The copper panel substrate 32 is selectively etched and electrolytically plated with a suitable metal, such as silver (Ag) or successive layers of nickel (Ni), palladium (Pd) and then gold (Au). The resulting leadframe strip is shown in
As best shown in
Referring now to
Next, the heat sink array is fixed to the leadframe strip using an electrically non-conductive adhesive. Referring to
A singulated semiconductor die 24 is conventionally mounted to the central cavity 36 of the heat sink 22, as shown in
The semiconductor die 24, wire bonds 28, the ground ring 42, the power ring 40 and the interior portions 34 of the contacts 26 are then encapsulated in a molding material 30 and the exposed surface of each of the contacts 24 is electrolytically plated with a layer of nickel (Ni). Finally the individual LPCC package 20 is singulated, resulting in the package shown in
Specific embodiments of the present invention have been shown and described herein. However, modifications and variations to these embodiments are possible. For example, the size and shape of many of the features of the LPCC package can vary while still performing the same function. Rather than selectively etching to form the leadframe, the leadframe can be formed by stamping. Similarly, rather than selectively etching to form the heat sink, the heat sink can also be formed by stamping. The leadframe strip can be selectively plated rather than flood plating. Also, the plating is not limited to metals described as other suitable metals can be plated onto the strip. Further, rather than using a double-sided adhesive film tape to fix the heat sink to the contacts, an electrically non-conductive epoxy can be screen printed on the heat sink, followed by placing the leadframe strip on the heat sink and oven curing the epoxy. Other methods of singulation are also possible such as die punching.
Those skilled in the art may conceive of still other modifications and variations. All such modifications and variations are believed to be within the sphere and scope of the present invention.
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