This disclosure relates to integrated circuit fabrication, and more particularly to a field effect transistor with a strained structure.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin field effect transistor (FinFET). A typical FinFET is fabricated with a thin vertical “fin” (or fin structure) extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. Having a gate on both sides of the channel allows gate control of the channel from both sides. Further advantages of FinFET comprise reducing the short channel effect and enabling higher current flow.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, an ordered atomic arrangement does not exist due to lattice mismatch between the portion 104 of the fin 104/108 and strained portions 108. Thus, strain-induced crystal defects 108a may become embedded in the strained structure 108. The crystal defects 108a may provide carrier transportation paths during device operation, thereby increasing the likelihood of device instability and/or device failure.
Accordingly, what are needed are methods for fabricating a reduced-defect strained structure.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Referring to
Referring to
Referring to
The substrate 102 may alternatively be made of some other suitable elementary semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Further, the substrate 102 may include an epitaxial layer (epi-layer), may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure.
The fin structure 104, formed over the substrate 102, comprises one or more fins. In the present embodiment, for simplicity, the fin structure 104 comprises a single fin. The fin comprises any suitable material, for example, the fin structure 104 comprises silicon. The fin structure 104 may further comprise a capping layer disposed on the fin, which may be a silicon-capping layer.
The fin structure 104 is formed using any suitable process comprising various deposition, photolithography, and/or etching processes. An exemplary photolithography process may include forming a photoresist layer (resist) overlying the substrate 102 (e.g., on a silicon layer), exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a masking element including the resist. The masking element may then be used to etch the fin structure 104 into the silicon layer. The fin structure 104 may be etched using reactive ion etching (RIE) processes and/or other suitable processes. In an example, the silicon fin 104 is formed by using patterning and etching of a portion of the silicon substrate 102. In another example, silicon fins of the fin structure 104 may be formed by using patterning and etching of a silicon layer deposited overlying an insulator layer (for example, an upper silicon layer of a silicon-insulator-silicon stack of an SOI substrate).
Isolation structure 106 may be formed on the substrate 102 to isolate the various doped regions. The isolation structure 106 may utilize isolation technology, such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI), to define and electrically isolate the various doped regions. In the present embodiment, the isolation structure 106 includes a STI. The isolation structure 106 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-K dielectric material, and/or combinations thereof. The isolation structure 106, and in the present embodiment, the STI, may be formed by any suitable process. As one example, the formation of the STI may include patterning the semiconductor substrate 102 by a conventional photolithography process, etching a trench in the substrate 102 (for example, by using a dry etching, wet etching, and/or plasma etching process), and filling the trench (for example, by using a chemical vapor deposition process) with a dielectric material. In some embodiments, the filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.
Still referring to
In one example, the gate dielectric layer 112 and gate electrode layer 114 are sequentially deposited on the substrate 102 and over a portion of the fin structure 104. In some embodiments, the gate dielectric layer 112 may include silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric. High-k dielectrics comprise metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. In the present embodiment, the gate dielectric layer 112 is a high-k dielectric layer with a thickness in the range of about 10 to 30 angstroms. The gate dielectric layer 112 may be formed using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. The gate dielectric layer 112 may further comprise an interfacial layer (not shown) to reduce damage between the gate dielectric layer 112 and the fin structure 104. The interfacial layer may comprise silicon oxide.
In some embodiments, the gate electrode layer 114 may comprise a single layer or multilayer structure. In the present embodiment, the gate electrode layer 114 may comprise poly-silicon. Further, the gate electrode layer 114 may be doped poly-silicon with uniform or non-uniform doping. Alternatively, the gate electrode layer 114 may include a metal such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, other conductive materials with a work function compatible with the substrate material, or combinations thereof. In the present embodiment, the gate electrode layer 114 comprises a thickness in the range of about 30 nm to about 60 nm. The gate electrode layer 114 may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof.
Then, a layer of photoresist is formed over the gate stack 110 by a suitable process, such as spin-on coating, and patterned to form a patterned photoresist feature by a proper lithography patterning method. In one embodiment, a width of the patterned photoresist feature is in the range of about 15 to 45 nm. The patterned photoresist feature can then be transferred using a dry etching process to the underlying layers (i.e., the gate electrode layer 114 and the gate dielectric layer 112) to form the gate stack 110. The photoresist layer may be stripped thereafter.
In another example, a hard mask layer 116 is formed over the gate stack 110; a patterned photoresist layer is formed on the hard mask layer 116; the pattern of the photoresist layer is transferred to the hard mask layer 116 and then transferred to the gate electrode layer 114 and the gate dielectric layer 112 to form the gate stack 110. The hard mask layer 116 comprises silicon oxide. Alternatively, the hard mask layer 116 may optionally comprise silicon nitride, silicon oxynitride, and/or other suitable dielectric materials, and may be formed using a method such as CVD or PVD. The hard mask layer 116 has a thickness in the range from about 100 to 800 angstroms.
Still referring to
Still referring to
Referring to
Referring to
Referring to
Referring to
In the present embodiment, the first strained layer 136 is disposed between the isolation structure 106 and the remaining sidewall portion 132w of the dielectric film 132. In an embodiment, a top surface 136b of the first strained layer 136 and the top surface 132a of the remaining sidewall portion 132w of the dielectric film 132 are substantially aligned. In another embodiment, the top surface 136b of the first strained layer 136 and the top surface 132a of the remaining sidewall portion 132w of the dielectric film 132 are below a top surface 106a of the isolation structure 106.
Referring to
In one embodiment, the second strained layer 138, such as silicon carbide (SiC), is epi-grown by a LPCVD process to form the source and drain regions of the n-type FinFET. An example the LPCVD process for the growth of SiC is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH.sub.4 and CH.sub.4 as reaction gases. In another embodiment, the second strained layer 138, such as silicon germanium (SiGe), is epi-grown by a LPCVD process to form the source and drain regions of the p-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH.sub.4 and GeH.sub.4 as reaction gases. In still another embodiment, the second strained layer 138, such as silicon, is epi-grown by a LPCVD process to form the source and drain regions of both the p-type FinFET and n-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH.sub.4 as a reaction gas.
Alternatively,
Referring to
Referring to
Referring to
In the present embodiment, the first strained layer 146 is disposed between the isolation structure 106 and the remaining first sidewall portion 142w of the dielectric film 142. Further, the remaining second sidewall portion 142s of dielectric film 142 is between the first strained layer 146 and the isolation structure 106. In an embodiment, a top surface 146b of the first strained layer 146 and the top surfaces 142a, 142b of the remaining first and second sidewall portions 142w, 142s of the dielectric film 142 are substantially aligned. In another embodiment, the top surface 146b of the first strained layer 136 and the top surfaces 142a, 142b of the remaining first and second sidewall portions 142w, 142s of the dielectric film 142 are below the top surface 106a of the isolation structure 106.
Referring to
In one embodiment a second strained layer 148 comprising silicon carbide (SiC) is epi-grown by a LPCVD process to form the source and drain regions of the n-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH.sub.4 and CH.sub.4 as reaction gases. In another embodiment a second strained layer 148 comprising silicon germanium (SiGe) is epi-grown by a LPCVD process to form the source and drain regions of the p-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH.sub.4 and GeH.sub.4 as reaction gases. In still another embodiment a second strained layer 148 comprising silicon is epi-grown by a LPCVD process to form the source and drain regions of both the p-type FinFET and n-type FinFET. The LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 200 Torr, using SiH.sub.4 as a reaction gas.
After the steps shown in
One aspect of this description relates to a field effect transistor. The field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
Another aspect of this description relates to a method for fabricating a semiconductor device. The method includes forming a recess cavity comprising an upper portion and a lower portion in a substrate, wherein the recess cavity includes a sidewall defined by an isolation structure. The method further includes forming a dielectric film on a bottom portion and a sidewall of the recess cavity opposite the isolation structure. The method further includes removing the dielectric film on the bottom portion of the recess cavity. The method further includes forming a first strained layer in the lower portion of the recess cavity in direct contact with the dielectric film, wherein the first strained layer is between the dielectric film and the isolation structure. The method further includes forming a second strained layer over the first strained layer in the upper portion of the recess cavity.
Still another aspect of this description relates to a field effect transistor. The field effect transistor includes an isolation structure in a substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate, wherein a sidewall of the S/D recess cavity is defined by the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a defect trapping layer, wherein the first defect trapping layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the defect trapping layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a strained layer overlying the defect trapping layer.
While the preferred embodiments have been described by way of example, it is to be understood that the disclosure is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the disclosure should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. The disclosure can be used to form or fabricate a strained structure for a semiconductor device. In this way, a strained structure having no defect in a semiconductor device is fabricated.
The present application is a continuation of U.S. application Ser. No. 14/844,247, filed Sep. 3, 2015, which is a continuation of U.S. application Ser. No. 13/910,633, filed Jun. 5, 2013, now U.S. Pat. No. 9,147,594, which is a continuation of U.S. application Ser. No. 12/775,006, filed May 6, 2010, now U.S. Pat. No. 8,497,528, issued Jul. 30, 2013, the disclosures of which are incorporated herein by reference in their entireties. The present application is related to U.S. patent application Ser. No. 12/707,788, filed on Feb. 18, 2010, titled MEMORY POWER GATING CIRCUIT AND METHODS; Ser. No. 12/758,426, filed on Apr. 12, 2010, titled FINFETS AND METHODS FOR FORMING THE SAME; Ser. No. 12/731,325, filed on Mar. 25, 2010, titled ELECTRICAL FUSE AND RELATED APPLICATIONS; Ser. No. 12/724,556, filed on Mar. 16, 2010, titled ELECTRICAL ANTI-FUSE AND RELATED APPLICATIONS; Ser. No. 12/757,203, filed on Apr. 9, 2010, titled STI STRUCTURE AND METHOD OF FORMING BOTTOM VOID IN SAME; Ser. No. 12/797,839, filed on Jun. 10, 2010, titled FIN STRUCTURE FOR HIGH MOBILITY MULTIPLE-GATE TRANSISTOR; Ser. No. 12/831,842, filed on Jul. 7, 2010, titled METHOD FOR FORMING HIGH GERMANIUM CONCENTRATION SiGe STRESSOR; Ser. No. 12/761,686, filed on Apr. 16, 2010, titled FINFETS AND METHODS FOR FORMING THE SAME; Ser. No. 12/766,233, filed on Apr. 23, 2010, titled FIN FIELD EFFECT TRANSISTOR; Ser. No. 12/757,271, filed on Apr. 9, 2010, titled ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF; Ser. No. 12/694,846, filed on Jan. 27, 2010, titled INTEGRATED CIRCUITS AND METHODS FOR FORMING THE SAME; Ser. No. 12/638,958, filed on Dec. 14, 2009, titled METHOD OF CONTROLLING GATE THICKNESS IN FORMING FINFET DEVICES; Ser. No. 12/768,884, filed on Apr. 28, 2010, titled METHODS FOR DOPING FIN FIELD-EFFECT TRANSISTORS; Ser. No. 12/731,411, filed on Mar. 25, 2010, titled INTEGRATED CIRCUIT INCLUDING FINFETS AND METHODS FOR FORMING THE SAME; Ser. No. 12/775,006, filed on May 6, 2010, titled METHOD FOR FABRICATING A STRAINED STRUCTURE; Ser. No. 12/886,713, filed Sep. 21, 2010, titled METHOD OF FORMING INTEGRATED CIRCUITS; Ser. No. 12/941,509, filed Nov. 8, 2010, titled MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION; Ser. No. 12/900,626, filed Oct. 8, 2010, titled TRANSISTOR HAVING NOTCHED FIN STRUCTURE AND METHOD OF MAKING THE SAME; Ser. No. 12/903,712, filed Oct. 13, 2010, titled FINFET AND METHOD OF FABRICATING THE SAME; 61/412,846, filed Nov. 12, 2010, 61/394,418, filed Oct. 19, 2010, titled METHODS OF FORMING GATE DIELECTRIC MATERIAL and 61/405,858, filed Oct. 22, 2010, titled METHODS OF FORMING SEMICONDUCTOR DEVICES.
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Number | Date | Country | |
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20170148917 A1 | May 2017 | US |
Number | Date | Country | |
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Parent | 14844247 | Sep 2015 | US |
Child | 15425552 | US | |
Parent | 13910633 | Jun 2013 | US |
Child | 14844247 | US | |
Parent | 12775006 | May 2010 | US |
Child | 13910633 | US |