Method for manufacturing a substrate with cavity

Information

  • Patent Application
  • 20070190764
  • Publication Number
    20070190764
  • Date Filed
    February 15, 2007
    17 years ago
  • Date Published
    August 16, 2007
    16 years ago
Abstract
An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the-upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:



FIG. 1 is a sectional view of a package on package according to the prior art.



FIG. 2 is a schematic sectional view of a semiconductor package constituting a package on package according to an embodiment of the present invention.



FIG. 3 is a sectional view of a package on package according to an embodiment of the present invention.



FIG. 4 is a flowchart illustrating a method for manufacturing a package on package according to an embodiment of the present invention.



FIGS. 5 to 7 are sectional views showing a manufacturing process of a package on package according to an embodiment of the present invention.


Claims
  • 1. A method for manufacturing a substrate with a cavity, the method comprising: (a) forming an upper layer circuit on an upper seed layer;(b) laminating a dry film on a portion of the upper seed layer where a cavity is to be formed;(c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit;(d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed;(e) removing the upper seed layer; and(f) forming the cavity by removing the dry film.
  • 2. The method of claim 1 further comprising: (g) forming a lower layer circuit on a lower seed layer;(h) forming a lower outer layer by laminating an insulation layer on top of the lower seed layer and on top and sides of the lower layer circuit;(i) laminating the lower outer layer on the other side of a core layer on which the internal circuit is formed; and(j) removing the lower seed layer.
  • 3. The method of claim 1, wherein the step (c) further comprising: forming a depression in the portion where the cavity is to be formed; and laminating the insulation layer on the upper seed layer by accommodating the dry film in the depression of the insulation layer.
  • 4. The method of claim 1 further comprising forming a bonding pad that is electrically connected with a semiconductor chip in the cavity.
  • 5. A substrate with a cavity comprising: a core layer having an internal circuit formed on both sides of an insulating material;an upper outer layer that is formed on one side of the core layer and in which an upper layer circuit is formed; anda lower outer layer that is formed on the other side of the core layer and in which a lower layer circuit is formed; wherein the upper outer layer further comprisesan insulation layer that is extended to sides of the upper layer circuit, and in which a depression is formed to accommodate a semiconductor chip.
  • 6. The substrate with a cavity of claim 5 further comprising a bonding pad that is formed on an upper surface of the core layer and is accommodated in the depression of the insulation layer to be electrically connected with the semiconductor chip.
Priority Claims (1)
Number Date Country Kind
10-2006-0014918 Feb 2006 KR national