This application is a national stage of Application No. PCT/AT2014/050300, filed Dec. 12, 2014, which application claims priority to Austrian Application No. A 50821/2013, filed on Dec. 12, 2013, the disclosures of which are hereby incorporated by reference in their entireties
The present invention relates to a method for embedding a component in a printed circuit board, or in a printed circuit board intermediate product, wherein the printed circuit board, or the printed circuit board intermediate product, comprises at least one insulating layer made of a prepreg material, and the component is fixed by the resin of the prepreg material, and to a printed circuit board or a printed circuit board intermediate product.
Printed circuit boards are used to fix and electrically connect electronic components and to connect these, in the form of a module, in electronic devices. Printed circuit boards are generally composed of a plurality of alternating layers made of insulating material and conducting material, wherein the layers made of electrically conducting material, such as copper, are structured to form conductor tracks, which are connected to the contact pads of the electronic components and route these accordingly. In addition to fixing and connecting the electronic components to each other, printed circuit boards can additionally assume a static function in an electronic device given the relatively high mechanical stability of the same.
In keeping with the steadily progressing miniaturization of electronic devices, such as mobile telephones, tablet computers and the like, the increasingly smaller electronic components are not only mounted and soldered to the surface of printed circuit boards, but also integrated into the interior, the cross-section of the printed circuit boards, to an ever greater extent. A conventional method for embedding electronic components in printed circuit boards provides for the creation of clearances or holes in the printed circuit board having the size and shape of the component to be embedded so that, in a subsequent step, the components can be inserted in the respective holes and glued in place there. The disadvantage of gluing the components in the printed circuit board, however, is that the adhesive necessarily represents a different material than the material of the insulating layer in the printed circuit board. While the insulating layers in the printed circuit board are made of prepreg materials, such as FR4, which is to say resin system, adhesives for inserting the components are usually solvent-based. The bonding of components therefore automatically results in inhomogeneities, wherein the relatively strong heating of the components in the printed circuit board during operation results in the formation of cracks over time due to differing coefficients of thermal expansion of the materials that are used, which adversely affects the durability of the printed circuit board, and thus of the corresponding electronic devices.
A method was therefore provided in WO 2012/100274 A1 in which the components are not fixed in the printed circuit board by way of adhesive, but fixation is achieved by way of the resin of the insulating layers of the printed circuit board. In the production of printed circuit boards, the insulating layers, which are made of a prepreg material, are joined to the conducting layers by lamination and compression at elevated temperatures. Prior to the lamination and compression at the elevated temperature, the resin of the prepreg materials is in a non-cured state, which is referred to as the B-stage. B-stage prepregs are stored on rollers while being cooled so as to prevent premature curing of the resin. The method according to WO 2012/100274 A1 now provides for clearances for the components to be created in a combination that comprises curable prepreg material, which is to say B-stage prepreg material, for the components to be mounted in the clearances, and the clearances or openings comprising the components to be covered with further B-stage prepreg layers, and optionally with further contact layers or electrically conducting layers. This combination is subsequently compressed to yield the finished printed circuit board, in which the prepreg material is present in the cured state, the cured state being referred to as the C-stage in professional circles.
The disadvantage with this method is the circumstance that covering the clearances comprising the components with further layers is necessarily required, so that the printed circuit boards produced by way of the method according to WO 2012/100274 A1 were relatively thick, which is contrary to the idea of miniaturization.
It is therefore the object of the invention to improve a method of the type mentioned above to the effect that the prepreg layers covering clearances and components can be avoided, whereby preferably thin printed circuit boards can be implemented.
So as to achieve this object, according to the invention a method of the type mentioned above is characterized by the following steps:
a) providing a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes at least one curable prepreg material;
b) creating a clearance in the combination for accommodating the component to be embedded;
c) covering at least the region of the clearance with a first temporary carrier layer on a first side of the combination;
d) positioning the component to be embedded in the clearance by way of the first temporary carrier layer;
e) covering at least the region of the clearance on the second side of the combination with a second temporary carrier layer;
f) compressing the combination comprising the component, curing the curable prepreg material; and
g) removing the temporary carrier layers.
The method according to the invention thus provides a combination of all the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes B-stage prepreg material, which is to say prepreg material that still must be cured, in contrast to already cured prepreg material. After the clearance for the component has been created, at least the region of the clearance according to step c) is covered with a first temporary carrier layer, so that the component to be embedded can be mounted on the first temporary carrier layer. Thereafter, the region of the clearance comprising the component positioned therein is covered on the second side of the combination with a second temporary carrier layer. A separating film may be used for this purpose, which may have any arbitrary design, as long as it can be removed after the prepreg material has cured and reached the C-stage. Curing of the prepreg material takes place in step f) and is carried out according to methods that are well-known in the prior art. The combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, comprising the mounted component and the two temporary carrier layers is generally subjected to mechanical pressure and simultaneous heating, whereby cross-linking of the resin of the prepreg material of the insulating layer or of the insulating layers takes place. During compressing according to step f), the resin of the prepreg material flows around the component, meets with a spatial delimitation at the temporary carrier layers, and thus also cures in the region of the components, resulting in a continuous resin phase through the prepreg layers forming the insulating layers of the printed circuit board, or of the printed circuit board intermediate product. In this way, only minor stresses develop during operation of the printed circuit board, as the components heat, which in the absence of an interface, as it occurs in the case of gluing between the adhesive and the resin, can be dissipated directly to the surrounding regions. Since the region of the embedded component did not have to be covered by additional prepreg layers so as to enable compressing, an extremely thin product is yielded after the temporary carrier layers have been removed in accordance with step g), which excellently meets today's requirements in regard to miniaturization.
The method according to the invention is defined with respect to one component that is being embedded. However, it is clear to a person skilled in the art that it is also possible in industrial production to embed a plurality of components in one and the same combination; however, the invention shall be understood such that only one component is inserted in each case in one clearance. The present description may therefore refer to the component in the singular form, or to a plurality of components, which does not change the meaning and the essence of the present invention.
The invention can be based on different types of a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product. According to a preferred variant of the method according to the invention, it is provided that the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, is composed of a plurality of layers made of a prepreg material. The use of such a combination in step a) of the method according to the invention results in a particularly homogeneous printed circuit board, or in a particularly homogeneous printed circuit board intermediate product, since no conducting layers are present between the layers made of a prepreg material, and the resin of the prepreg material can thus flow unimpaired prior to curing, and can consequently flow around the component to be embedded, or the components to be embedded. After compression and after removal of the temporary carrier layers, this preferred embodiment of the present invention generally requires for the wiring or the routing of the embedded component or components to take place in a subsequent processing step, in which conductor tracks are formed on the outsides according to known methods.
So as to simplify the formation of conductor tracks, the invention is refined according to one preferred embodiment to the effect that the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, is composed of a plurality of layers made of prepreg material and copper layers located on the outside on both sides. In this case, copper layers are provided on the outside of the printed circuit board, or of the printed circuit board intermediate product, on both sides after compression and after removal of the temporary carrier layers, from which suitable conductor tracks can be formed, for example using photolithography methods.
If the printed circuit board, or the printed circuit board intermediate product, which is to be produced by way of the method according to the invention, is to meet particular requirements in terms the mechanical stability, according to a preferred embodiment of the present invention the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, can be composed of a plurality of layers made of prepreg material and a central core. In professional circles, a core is understood to mean a layer of a cured prepreg material, such as FR4, having copper layers laminated thereon on both sides. Such cores can be procured industrially as a standard part and offer a certain stability in the method according to the invention already before compressing the curable prepreg material in the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, which results in improved handling during processing and increased strength of the finished product. The central core may optionally be appropriately structured for the formation of conductor tracks.
According to a further preferred embodiment of the present invention, the combination is composed of a plurality of layers made of prepreg material and a central core, as well as copper layers located on the outside on both sides, which corresponds to a combination of the two preceding variants, whereby a combination of the above-described advantages is achieved.
Moreover, it is conceivable according to a preferred embodiment of the present invention that the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, is composed of an inside layer made of a prepreg material and cores located on the outside on both sides.
The method according to the invention allows printed circuit boards, or printed circuit board intermediate products, comprising embedded components to be produced in a particularly thin manner. According to a preferred embodiment of the present invention, the method according to the invention is refined to the effect that the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, essentially has the thickness of the components to be embedded. Insufficient thickness would cause the components to protrude beyond the cross-section of the printed circuit board and consequently prevent these from being entirely encased by the resin of the prepreg material. However, a thickness of the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, that considerably exceeds the thickness of the components is likewise not necessary to ensure sufficient embedding into the resin of the prepreg material.
As was already mentioned above, the method according to the invention can be applied to a plurality of components, so that a plurality of components are embedded into the printed circuit board. It is essential, however, that the method, as it is defined in the main claim, is carried out for each individual component, so that in each case one clearance is created for a respective component to be embedded.
According to a preferred embodiment of the present invention, it is provided that components having differing thicknesses are mounted in the respective clearances, and the second temporary carrier layer is oriented with a non-adhering surface to the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product. In this case, the thickness of the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, is selected based on the thickest component, or based on the thickest components, so that thinner components do not extend completely through the cross-section of the combination. For this reason, the second temporary carrier layer must be oriented with a non-adhering surface to the combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, so as to prevent the component from being lifted off the first temporary carrier layer when an adhesive layer is compressed with the second temporary carrier layer.
The first side of the combination is preferably a contact side of the printed circuit board, or of the printed circuit board intermediate product, and the component to be embedded is fixed in the clearance face up with respect to this contact side.
According to a preferred refinement of the present invention, both the first side and the second side of the combination is a contact side of the printed circuit board. In this case, both sides of the printed circuit board can comprise conductor tracks, whereby a highly integrated and thus space-saving printed circuit board is obtained.
This is particularly advantageous when a component having contacts on two opposing sides of the component is being embedded, as is the subject matter of a preferred embodiment of the present invention. This configuration allows current to flow vertically, which is to say current to flow through the cross-section of the printed circuit board, wherein the electronic component serves as a current bridge.
The component is preferably selected from the group consisting an integrated circuit, an LED, a heat sink, a battery, and a printed circuit board, and in particular a multilayer printed circuit board. In particular, the aforementioned component can be any active or passive electronic part. In this connection, the electronic component can also be a fully or partially populated printed circuit board (module) or a MEMS- or MOEMS structure. However, the component may also be a non-electronic component, for example a cooling element, which in particular is made of a metallic material. It is obvious to a person skilled in the art that the method according to the invention can be used to embed any type of electronic component, so that this enumeration shall not be considered to be exhaustive.
According to a particularly preferred embodiment of the present invention, the component is an IMS component. The abbreviation IMS denotes “insulated metal substrate” and refers to a component in which a thin insulator layer, for example epoxy resin-based, is disposed between a thick, metallic base layer, for example made of aluminum or copper, and a relatively thin conducting layer, for example made of aluminum or copper. IMS components are used for contacting and the simultaneous cooling of power components, since the conducting layer, on the one hand, can be structured to obtain contact areas and conductor tracks and, on the other hand, is electrically insulated with respect to the base layer by the insulator layer, wherein the insulator layer ensures good heat transfer to the base layer where the heat developed by the power component can be dissipated.
The first temporary carrier layer is preferably designed in the form of an adhesive tape. The adhesive action of the adhesive tape positions or temporarily fastens the components, wherein however the second temporary carrier layer does not necessarily have to be an adhesive tape.
The invention will be described hereafter in greater detail based on one exemplary embodiment shown schematically in the drawings. In the drawings:
To carry out the method according to the invention, it is essentially only necessary to cover at least the region of the clearance, or the regions of the clearances, with a first temporary carrier layer 5. In industrial production, however, it is usually easier to cover not only the region or the regions of the clearances with a first temporary carrier layer, but the entire surface area of the combination 100 with a continuous first temporary carrier layer 5.
It is now apparent in
It is apparent from
According to a preferred embodiment of the present invention, in
The use of IMS parts is particularly suited for dissipating heat, and in the case shown in
Number | Date | Country | Kind |
---|---|---|---|
50821/2013 | Dec 2013 | AT | national |
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/AT2014/050300 | 12/12/2014 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
---|---|---|---|
WO2015/085342 | 6/18/2015 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
4931134 | Jacques et al. | Jun 1990 | A |
5206188 | Hiroi et al. | Apr 1993 | A |
5241456 | Marcinkiewicz et al. | Aug 1993 | A |
5561085 | Gorowitz et al. | Oct 1996 | A |
5645673 | Fasano et al. | Jul 1997 | A |
5730635 | De et al. | Mar 1998 | A |
6005289 | Watanabe | Dec 1999 | A |
6120693 | Petti et al. | Sep 2000 | A |
6309912 | Chou et al. | Oct 2001 | B1 |
6324067 | Nishiyama | Nov 2001 | B1 |
6442033 | Lu et al. | Aug 2002 | B1 |
6492726 | Ang | Dec 2002 | B1 |
6506632 | Cheng et al. | Jan 2003 | B1 |
6674159 | Peterson | Jan 2004 | B1 |
6687985 | Nishiyama | Feb 2004 | B2 |
6732428 | Kwong | May 2004 | B1 |
6815046 | Kumano | Nov 2004 | B2 |
6903458 | Nathan | Jun 2005 | B1 |
6919508 | Forcier | Jul 2005 | B2 |
7087991 | Chen et al. | Aug 2006 | B2 |
7154760 | Tsuchiya | Dec 2006 | B2 |
7282394 | Cho et al. | Oct 2007 | B2 |
7629204 | Hsu | Dec 2009 | B2 |
7705446 | Chia et al. | Apr 2010 | B2 |
7719104 | Hsu et al. | May 2010 | B2 |
7863735 | Cho et al. | Jan 2011 | B1 |
7894203 | Tsuda | Feb 2011 | B2 |
7947906 | Lee et al. | May 2011 | B2 |
7977579 | Bathan | Jul 2011 | B2 |
8049114 | Chen et al. | Nov 2011 | B2 |
8101868 | Ito et al. | Jan 2012 | B2 |
8130507 | Origuchi et al. | Mar 2012 | B2 |
8186045 | Sakamoto et al. | May 2012 | B2 |
8217509 | Horiuchi et al. | Jul 2012 | B2 |
8320135 | Ito et al. | Nov 2012 | B2 |
8354743 | Jensen | Jan 2013 | B2 |
8381394 | Shizuno | Feb 2013 | B2 |
8400776 | Sahara et al. | Mar 2013 | B2 |
8547701 | Tuominen et al. | Oct 2013 | B2 |
8563358 | Landesberger et al. | Oct 2013 | B2 |
8642465 | Schimetta et al. | Feb 2014 | B2 |
8736065 | Gonzalez et al. | May 2014 | B2 |
8785788 | Shimizu et al. | Jul 2014 | B2 |
8789271 | Zluc et al. | Jul 2014 | B2 |
8829357 | Mikado et al. | Sep 2014 | B2 |
8914974 | Lenhardt et al. | Dec 2014 | B2 |
9159693 | Choi | Oct 2015 | B2 |
9179553 | Suzuki | Nov 2015 | B2 |
9418930 | Stahr et al. | Aug 2016 | B2 |
9560769 | Shimabe et al. | Jan 2017 | B2 |
9648758 | Gotzinger et al. | May 2017 | B2 |
9713248 | Langer et al. | Jul 2017 | B2 |
9763337 | Jager et al. | Sep 2017 | B2 |
9781845 | Stahr et al. | Oct 2017 | B2 |
9820381 | Wang et al. | Nov 2017 | B2 |
10219384 | Stahr et al. | Feb 2019 | B2 |
20020036100 | Slemmons et al. | Mar 2002 | A1 |
20030015342 | Sakamoto et al. | Jan 2003 | A1 |
20030090883 | Asahi et al. | May 2003 | A1 |
20040014317 | Sakamoto et al. | Jan 2004 | A1 |
20040114652 | Yoshikawa | Jun 2004 | A1 |
20040168825 | Sakamoto et al. | Sep 2004 | A1 |
20040170766 | Inoue et al. | Sep 2004 | A1 |
20040233650 | Miyashita et al. | Nov 2004 | A1 |
20050017347 | Morimoto et al. | Jan 2005 | A1 |
20050103522 | Grundy et al. | May 2005 | A1 |
20050189640 | Grundy et al. | Sep 2005 | A1 |
20050190537 | Rossi et al. | Sep 2005 | A1 |
20050233122 | Nishimura et al. | Oct 2005 | A1 |
20060008970 | Oggioni et al. | Jan 2006 | A1 |
20060049530 | Hsu et al. | Mar 2006 | A1 |
20060101638 | Germann et al. | May 2006 | A1 |
20060120056 | Sasaki | Jun 2006 | A1 |
20060193108 | Usui et al. | Aug 2006 | A1 |
20060198570 | Ogawa et al. | Sep 2006 | A1 |
20060222285 | Minamio et al. | Oct 2006 | A1 |
20060231950 | Yoon | Oct 2006 | A1 |
20060278967 | Tuominen et al. | Dec 2006 | A1 |
20070069352 | Ho et al. | Mar 2007 | A1 |
20070131349 | Tuominen et al. | Jun 2007 | A1 |
20070166886 | Iihola et al. | Jul 2007 | A1 |
20080067666 | Hsu | Mar 2008 | A1 |
20080192443 | Hatanaka et al. | Aug 2008 | A1 |
20080192450 | Tuominen et al. | Aug 2008 | A1 |
20080196931 | Lee | Aug 2008 | A1 |
20080202801 | Tuominen et al. | Aug 2008 | A1 |
20080264687 | Park et al. | Oct 2008 | A1 |
20080283491 | Arai et al. | Nov 2008 | A1 |
20080296056 | Kinoshita et al. | Dec 2008 | A1 |
20090001609 | Lim | Jan 2009 | A1 |
20090014749 | Matsuda et al. | Jan 2009 | A1 |
20090026168 | Tsai et al. | Jan 2009 | A1 |
20090194318 | Yeon et al. | Aug 2009 | A1 |
20090205859 | Tanaka et al. | Aug 2009 | A1 |
20090241333 | He et al. | Oct 2009 | A1 |
20090277673 | Sohn | Nov 2009 | A1 |
20090293271 | Tanaka | Dec 2009 | A1 |
20100018761 | Wang et al. | Jan 2010 | A1 |
20100019368 | Shin | Jan 2010 | A1 |
20100084175 | Suzuki | Apr 2010 | A1 |
20100170703 | Iihola et al. | Jul 2010 | A1 |
20100252303 | Chang et al. | Oct 2010 | A1 |
20100282498 | Tezak et al. | Nov 2010 | A1 |
20110089531 | Hillman et al. | Apr 2011 | A1 |
20110127076 | Jeong et al. | Jun 2011 | A1 |
20110127675 | Ewe et al. | Jun 2011 | A1 |
20110183093 | Wada | Jul 2011 | A1 |
20110198018 | Schrittwieser et al. | Aug 2011 | A1 |
20110203836 | Yokota et al. | Aug 2011 | A1 |
20110212274 | Selsley et al. | Sep 2011 | A1 |
20110215464 | Guzek et al. | Sep 2011 | A1 |
20110259630 | Park | Oct 2011 | A1 |
20110272177 | Weichslberger et al. | Nov 2011 | A1 |
20110284267 | Chang | Nov 2011 | A1 |
20110290546 | Lee et al. | Dec 2011 | A1 |
20110304998 | Lin | Dec 2011 | A1 |
20110317381 | Kim et al. | Dec 2011 | A1 |
20120048605 | Chung | Mar 2012 | A1 |
20120091594 | Landesberger et al. | Apr 2012 | A1 |
20120153493 | Lee et al. | Jun 2012 | A1 |
20120181074 | Ishihara et al. | Jul 2012 | A1 |
20120247819 | Tsuyutani et al. | Oct 2012 | A1 |
20130146991 | Otremba et al. | Jun 2013 | A1 |
20130153269 | Takahashi et al. | Jun 2013 | A1 |
20130256884 | Meyer | Oct 2013 | A1 |
20140000941 | Weidinger et al. | Jan 2014 | A1 |
20140120291 | Kim et al. | May 2014 | A1 |
20140227834 | Karpman | Aug 2014 | A1 |
20140254119 | Im | Sep 2014 | A1 |
20150007934 | Götzinger et al. | Jan 2015 | A1 |
20150157862 | Greenberg et al. | Jun 2015 | A1 |
20150189763 | Schrittwieser | Jul 2015 | A1 |
20150334833 | Wang et al. | Nov 2015 | A1 |
20150334841 | Schmid et al. | Nov 2015 | A1 |
20150334844 | Shimabe et al. | Nov 2015 | A1 |
20150342062 | Jäger et al. | Nov 2015 | A1 |
20160021763 | Stahr et al. | Jan 2016 | A1 |
20160133558 | Stahr et al. | May 2016 | A1 |
20160353566 | langer et al. | Dec 2016 | A1 |
20170034923 | Lin et al. | Feb 2017 | A1 |
20170048984 | Weidinger et al. | Feb 2017 | A1 |
20170164481 | Stahr et al. | Jun 2017 | A1 |
20190082543 | Weidinger et al. | Mar 2019 | A1 |
20190150288 | Stahr et al. | May 2019 | A1 |
Number | Date | Country |
---|---|---|
13434 | Dec 2013 | AT |
100525591 | Aug 2009 | CN |
102293070 | Dec 2011 | CN |
103199069 | Jul 2013 | CN |
203072246 | Jul 2013 | CN |
19642488 | Apr 1998 | DE |
20021698 | Apr 2001 | DE |
20221189 | Jun 2005 | DE |
102006009723 | Sep 2007 | DE |
102008025223 | Dec 2008 | DE |
102008040906 | Feb 2010 | DE |
102010042567 | Mar 2012 | DE |
195935 | Oct 1986 | EP |
275433 | Jul 1988 | EP |
1225629 | Jul 2002 | EP |
1304742 | Apr 2003 | EP |
1424731 | Jun 2004 | EP |
2119327 | Oct 2011 | EP |
2822338 | Sep 2002 | FR |
2485087 | May 2012 | GB |
11150368 | Jun 1999 | JP |
2003031914 | Jan 2003 | JP |
2003198133 | Jul 2003 | JP |
2004031682 | Jan 2004 | JP |
2005333109 | Dec 2005 | JP |
2007189006 | Jul 2007 | JP |
2007318090 | Dec 2007 | JP |
2010206124 | Sep 2010 | JP |
2011138873 | Jul 2011 | JP |
2012044102 | Mar 2012 | JP |
2012151359 | Aug 2012 | JP |
101253514 | Apr 2013 | KR |
98205301 | May 1998 | WO |
03092344 | Nov 2003 | WO |
2005020651 | Mar 2005 | WO |
2005104636 | Nov 2005 | WO |
2006013230 | Feb 2006 | WO |
2006134217 | Dec 2006 | WO |
2007087660 | Aug 2007 | WO |
2008098271 | Aug 2008 | WO |
2008104324 | Sep 2008 | WO |
2009143550 | Dec 2009 | WO |
2010048654 | May 2010 | WO |
2010085830 | Aug 2010 | WO |
2011088489 | Jul 2011 | WO |
2011099820 | Aug 2011 | WO |
2012016258 | Feb 2012 | WO |
2012065202 | May 2012 | WO |
2012100274 | Aug 2012 | WO |
2013029073 | Mar 2013 | WO |
2013029074 | Mar 2013 | WO |
2014131071 | Sep 2014 | WO |
2014197917 | Dec 2014 | WO |
2015077808 | Jun 2015 | WO |
2015085342 | Jun 2015 | WO |
2015113088 | Aug 2015 | WO |
2015127489 | Sep 2015 | WO |
Entry |
---|
Written Opinion for International Application No. PCT/AT2014/050300, Search completed Mar. 13, 2015, dated Mar. 23, 2015, 7 Pgs. |
International Preliminary Report on Patentability for International Application No. PCT/AT2014/050239, Report issued Mar. 1, 2016, dated Jun. 1, 2016, 9 Pgs. |
International Preliminary Report on Patentability for International Application PCT/AT2014/050113, Report issued Aug. 28, 2015, dated Aug. 28, 2015, 8 Pgs. |
International Preliminary Report on Patentability for International Application PCT/AT2015/050019, Report issued Aug. 2, 2016, dated Aug. 11, 2016, 8 Pgs. |
International Search Report and Written Opinion for International Application No. PCT/AT2014/050239, Search completed Feb. 2, 2015, dated Feb. 9, 2015, 8 Pgs. |
International Search Report and Written Opinion for International Application No. PCT/AT2015/050019, Search completed Apr. 23, 2015, dated May 27, 2015, 9 Pgs. |
International Search Report for International Application PCT/AT2014/050113, Report completed Aug. 22, 2014, dated Aug. 28, 2014, 3 Pgs. |
Written Opinion for International Application PCT/AT2014/050113, Report completed Aug. 22, 2014, dated Aug. 28, 2014, 6 Pgs. |
Charboneau, B C et al., “Double-Sided Liquid Cooling for Power Semiconductor Devices Using Embedded Power Packaging”, IEEE Transactions on Industry Applications, IEEE Service Center, vol. 44, No. 5, Sep. 1, 2008, pp. 1645-1655, XP011446042, ISSN: 0093-994, DOI: 10.1109/TIA.2008.2002270. |
Jian, Yin, “High Temperature SiC Embedded Chip Module (ECM) with Double-sided Metallization Structure”, Jan. 3, 2006, XP055135318, Gefunden im Internet: URL:http://hdl.handle.net/ 10919/30076. |
Mital et al., “Thermal Design Methodology for an Embedded Power Electronic Module Using Double-Sided Microchannel Cooling”, Journal of Electric Packaging, ASME International, US, vol. 130, No. 3, Sep. 1, 2008, XP008171354, DOI: 10.1115/1.2957320, Retrieved on Jul. 29, 2008. |
Pang, Y et al., “Assessment of Some Integrated Cooling Mechanisms for an Active Integrated Power Electronics Module”, Journal of Electronic Packaging, ASME International, US, vol. 129, No. 1, Mar. 1, 2007, pp. 1-8, XP008171355, ISSN: 1 043-7398, DOI: 1 0.1115/1.2429703. |
Austrian Search Report for Application No. A 740/2012, Filing Date Jul. 7, 2012, Search Completed May 3, 2013, 2 pgs. |
International Preliminary Report on Patentability for International Application No. PCT/AT2013/000029, Report issued Aug. 26, 2014, dated Sep. 4, 2014, 13 Pgs. |
International Preliminary Report on Patentability for International Application No. PCT/AT2013/050260, Report issued Mar. 27, 2015, dated Mar. 27, 2015, 8 Pgs. |
International Preliminary Report on Patentability for International Application No. PCT/AT2013/050262, Report issued Mar. 11, 2015, dated Mar. 11, 2015, 14 Pgs. |
International Preliminary Report on Patentability for International Application No. PCT/AT2013/050128, Report completed Sep. 16, 2014, 11 Pgs. |
International Preliminary Report on Patentability for International Application No. PCT/AT2013/050249, Report issued Jun. 30, 2015, dated Jul. 9, 2015, 6 Pgs. |
International Preliminary Report on Patentability for International Application PCT/AT2014/050044, Report Completed Jun. 23, 2015, dated Jun. 23, 2015, 18 Pgs. |
International Preliminary Report on Patentability for International Application PCT/AT2015/050052, Report issued Jun. 6, 2016, dated Dec. 23, 2015, 16 Pgs. |
International Search Report and Written Opinion for International Application No. PCT/AT2013/050262, Search completed Mar. 18, 2014, dated Mar. 27, 2014, 9 Pgs. |
International Search Report and Written Opinion for International Application No. PCT/AT2014/050044, Search completed May 9, 2014, dated May 20, 2014, 9 Pgs. |
International Search Report and Written Opinion for International Application No. PCT/AT2015/050052, Search completed May 26, 2015, dated Jun. 2, 2015, 10 Pgs. |
International Search Report for International Application No. PCT/AT2013/050128, International Filing Date Jun. 25, 2013, Search Completed Oct. 23, 2013, dated Nov. 26, 2013, 6 pgs. |
International Search Report for International Application No. PCT/AT2013/050249, Search completed Apr. 1, 2014, dated Sep. 4, 2014, 4 Pgs. |
International Search Report for International Application No. PCT/AT2013/050260, Search completed Apr. 29, 2014, dated May 13, 2014, 4 Pgs. |
International Search Report for International Application PCT/AT2013/000029, completed May 31, 2013, 6 pgs. |
Written Opinion for International Application PCT/AT2013/000029, 5 pgs. |
Written Opinion for International Application No. PCT/AT2013/050128, Search Completed Oct. 23, 2013, dated Nov. 26, 2013, 5 pgs. |
Written Opinion for International Application No. PCT/AT2013/050249, Search completed Apr. 1, 2014, dated Sep. 4, 2014, 5 Pgs. |
Written Opinion for International Application No. PCT/AT2013/050260, Search completed Apr. 29, 2014, dated May 13, 2014, 4 Pgs. |
International Search Report for International Application No. PCT/AT2014/050300, Search completed Mar. 13, 2015, dated Mar. 23, 2015, 3 Pgs. |
International Preliminary Report on Patentability for International Application PCT/AT2014/050300, Report issued Oct. 10, 2015, dated Mar. 23, 2016, 9 Pgs. |
Office Action dated Sep. 18, 2014 of the corresponding Austrian priority patent application No. A 50821/2013. |
Number | Date | Country | |
---|---|---|---|
20160324004 A1 | Nov 2016 | US |