The present disclosure is related to stacked-die microelectronic packages with small footprints and associated methods of manufacturing.
Microelectronic dies are typically manufactured on semiconductor wafers or other types of workpieces using sophisticated equipment and processes. The individual dies generally include a plurality of bond-pads coupled to integrated circuits. The bond-pads provide external contacts through which supply voltage, data signals, and other electrical signals are transmitted to/from the integrated circuits. The bond-pads are usually very small, and they are typically arranged in dense arrays separated by a fine pitch. The wafers and dies can also be quite delicate. As a result, the dies are packaged for protection and for connecting the bond-pads to arrays of larger terminals that can be soldered to printed circuit boards.
One challenge of manufacturing microelectronic devices is to cost effectively package the dies. Electronic product manufacturers are under continuous pressure to reduce the size of their products. Accordingly, microelectronic die manufacturers seek to reduce the size of the packaged dies incorporated into the electronic products.
The microelectronic device package 100 typically has a large footprint to accommodate the wirebonding of the second die 102b to the substrate 101. As shown in
Specific details of several embodiments of the disclosure are described below with reference to microelectronic device packages with small footprints and associated methods of manufacturing. Typical microelectronic device packages include microelectronic circuits or components, thin-film recording heads, data storage elements, microfluidic devices, and other components manufactured on microelectronic substrates. Micromachines and micromechanical devices are included within this definition because they are manufactured using technology similar to that used in the fabrication of integrated circuits. Substrates can be semiconductor pieces (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive pieces (e.g., various ceramic substrates), or conductive pieces. A person skilled in the relevant art will also understand that the disclosure may have additional embodiments, and that the disclosure may be practiced without several of the details of the embodiments described below with reference to
The first die 202a includes a first active surface 203a opposite a first backside surface 203b. The second die 202b includes a second active surface 205a opposite a second backside surface 205b. The first die 202a can be an upper die, and the second die 202b can be a lower die. The first die 202a has a first footprint (e.g., as characterized by a width, a length, a diameter, and/or another dimension) larger than a second footprint of the second die 202b. In certain embodiments, the second footprint of the second die 202b can be substantially within the first footprint of the first die 202a. For example, in the illustrated embodiment, the first and second footprints are generally centered relative to each other. In other embodiments, the second footprint may be offset from the first footprint of the first die 202a. In a particular embodiment, the first die 202a includes a memory device (e.g., DRAM), and the second die 202b includes a logic processor and/or other suitable processing components. In other embodiments, the first and second dies 202a and 202b can include other electrical and/or mechanical components.
The microelectronic device package 200 can also include first wirebonds 210a between first terminals 208a on the substrate 201 and first bond sites 212a on the first die 202a. Second wirebonds 210b extend between second terminals 208b on the substrate 201 and second bond sites 212b on the second die 202b. The first wirebonds 210a are outboard of the corresponding second wirebonds 210b. The first wirebonds 210a also have a first wirebond length greater than a second wirebond length of the second wirebonds 210b.
The microelectronic device package 200 can also include a first adhesive 204a and a second adhesive 204b. The first adhesive 204a is disposed between the first backside surface 203b of the first die 202a and the second active surface 205a of the second die 202b. The first adhesive 204a is also disposed between the first surface 201a of the substrate 201 and the perimeter portion of the first backside surface 203b that extends laterally beyond the second footprint of the second die 202b. The second adhesive 204b (e.g., an epoxy) is disposed between the second backside 205b of the second die 202b and the first surface 201a of the substrate 201. In certain embodiments, the first adhesive 204a can include a film-over-wire adhesive and/or other suitable types of adhesive. One suitable film-over-wire adhesive includes a die-attach film (Model No. ELEP MOUNT EM-310) provided by Nitto Denko Corp. of Osaka, Japan. In other embodiments, the first adhesive 204a can include an epoxy and/or other non-conductive material.
In certain embodiments, the first adhesive 204a can substantially or even completely encapsulate the second die 202b, the second wirebonds 210b, the second bond sites 212b, and the second terminals 208b. For example, the first adhesive 204a can include a first portion 207a adjacent to and outboard of a second portion 207b. The first portion 207a is between the first die 202a and the substrate 201. The second portion 207b is between the first die 202a and the second die 202b and generally corresponds to the second footprint of the second die 202b. The first portion 207a couples the first die 202a to the substrate 201, and the second portion 207b couples the first die 202a to the second die 202b. The first portion 207a has a thickness greater than that of the second portion 207b.
The first adhesive 204a can have an overall height greater than the combined height of the second die 202b, the second adhesive 204b, and the loop height of the second wirebonds 210b. The phrase “loop height” generally refers to the height between the top of a wirebond and the surface of a corresponding die. The first adhesive 204a can also have an overall width greater than that of the second die 202b and the distance between the second terminals 208a such that the second terminals 208a are at least proximately inboard of the first die 202a. In the illustrated embodiment, the first adhesive 204a has a footprint generally equal to that of the first die 202a. In other embodiments, the first adhesive 204a can also have a footprint that is greater or less than that of the first die 202a. In further embodiments, the first adhesive 204a can partially encapsulate at least one of the second terminals 208b and the second wirebonds 210b. In yet further embodiments, the package 200 can include additional non-conductive layers between the first and second dies 202a and 202b, as described in more detailed below with reference to
Several embodiments of the package 200 can have a smaller footprint and shorter wirebond lengths than in conventional packages (e.g., the package 100 shown in
Several embodiments of the package 200 can also enable wirebonding the second die 202b with a bond site layout that is more flexible than in conventional packages. For example, in the package 100 of
Several embodiments of the package 200 can further reduce electrical and/or electromagnetic interference between the first and second dies 202a and 202b. The inventors have recognized that the second die 102b in
As illustrated in
Several embodiments of the process described above with reference to
The process described above with reference to
In further embodiments, the first die 202a, the second die 202b, and the substrate 201 can have other arrangements. For example, as illustrated in
Even though only one first die 202a is illustrated in
Individual microelectronic device packages 200 may be incorporated into myriad larger and/or more complex systems. A representative system 300 is shown schematically in
From the foregoing, it will be appreciated that specific embodiments of the disclosure have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, many of the members of one embodiment may be combined with other embodiments in addition to or in lieu of the members of the other embodiments. Accordingly, the disclosure is not limited except as by the appended claims.
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