Patent Application
20120068334
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2010-212781, filed on Sep. 22, 2010; the entire contents of which are incorporated herein by reference.
The embodiments relate in general to semiconductor devices and manufacturing methods thereof.
Recently, it is required to improve an operation speed of a device and to increase a capacity of a memory to achieve high integration and sophisticated function of a semiconductor device. In some devices, a chip, in which logic and a large capacity DRAM are packaged by Chip on Chip (CoC) connection, has been developed in place of one chip eDRAM.
When a minute bump for CoC connection is formed, a bump having a high aspect ratio may be required in consideration of CoC properties. At the time, a solder bump is formed via a pillar of Cu, Ni, Au, and the like. In the CoC connection, the bump pitch is recently more miniaturized and is becoming to 40 μm, 30μm.
Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.
The semiconductor devices and manufacturing methods of the semiconductor devices according to the embodiments will be explained below in detail referring to the accompanying drawings. The present invention is not limited to the following embodiments.
First, as illustrated in
Cu is used as uppermost layers of the under bump metals 4 and the uppermost layers function as power distribution layers in a plating process which is a subsequent process. Next, to form a bump pattern, a photosensitive resist 5 is applied, exposure is performed using a photomask 6 as a mask, and a desired bump pattern is formed using a photolithography technology. As the photosensitive resist 5, for example, a negative resist is used.
Since a special opening shape can be formed by mainly and largely changing a focus condition in exposure of the photolithography technology from an ordinary straight shape (
Next, a Ni pillar 7 is formed by precipitating Ni on the under bump metal 4 of a bump pattern portion by electrolytic plating and subsequently a solder 8 is precipitated by electrolytic plating. Subsequently, the photosensitive resist 5 is removed by a stripping liquid, and the under bump metal 4 is removed by etching. Thereafter, the solder 8 is melted and condensed again by a reflow process, and a solder bump 8′ is formed. At the time, since the exposure is performed by greatly changing the photolithography process from a focus value of 8 μm at which the ordinary straight shape can be obtained to the focus value of 16 μm, a bump shape which spreads toward a bottom can be obtained as illustrated in
In general, a shift of a focus value in exposure from a small value to large value causes the angle between a bottom surface and a side surface of a bump shape with respect to a bump side (a of
In a bump bottom diameter B at the time, a shape, which is 3.6 μm larger than 20 μm at which the straight shape is exposed, is obtained. When the solder bump 8′ having the above shape is formed, since the bottom area of an interface between the pillar 7 under the solder 8 and the under bump metal 4 of a ground layer can be kept about 40 larger, an intimate contact property can be improved. Further, since the top diameter T of the solder bump 8′ can be kept smaller than the bottom diameter B with respect to the bump pitch of 40 μm or less, a short-circuit risk to an adjacent bump can be reduced. As a result, even if a bump is greatly miniaturized, a solder bump having high reliability can be formed. As illustrated in
Note that it is preferable that the ratio T:B of the top diameter T and the bottom diameter B is 1:1 to 1:4 or the angle α between the bottom surface and the side surface of the bump shape with respect to the bump side is 45°<α<90°. Further, it is more preferable that both the ratio T:B and the angle a are within the above ranges.
This is because when the ratio T:B is out of the range and B becomes smaller than T or when a is out of the range and becomes 90° or more, the bottom diameter B of the bump becomes thin and the intimate contact area of the bump with the interface of the ground layer becomes small. Further, this is because a problem arises in that the top diameter T of the bump becomes relatively too large and a short-circuit risk increases when the bump is connected.
Further, this is because when B becomes four times as large as T or when a becomes 45° or less on the contrary, since the bottom diameter B of the bump becomes too thick, a short-circuit risk to an adjacent bump becomes high. Further, this is because a problem arises in that since the top diameter T of the bump becomes too small, it becomes very difficult to connect the bump.
Further, when a case, in which it is intended to increase the degree of integration of the bump, and the like are also taken into consideration, in order to reduce the short-circuit risk to the adjacent bump, it is more preferable that the ratio T:B of the top diameter T and the bottom diameter B is 1:1 to 1:3 or the angle a between the bottom surface and the side surface of the bump shape with respect to the bump side is 55°<α<90°. Further, it is more preferable that both the ratio T:B and the angle a are within the above range.
As described above, when the bump of the embodiment is formed on a semiconductor substrate on which a semiconductor device is formed, even if the pitch of the bump is formed in an ultra-minute pattern, an intimate contact property of the bump with the ground layer can be improved, a short-circuit risk between solder bumps can be reduced, and the reliability of a semiconductor package can be improved.
In a second embodiment of the invention, for example, a positive resist is used as a photosensitive resist 5, a focus value in exposure of a photolithography process is set to 28 μm (a first focus value) which is larger than the focus value in the first embodiment (
As a bump bottom diameter B at the time, a shape 16.0 μm larger than 20 μm when a straight shape is exposed can be obtained. As illustrated in
Different from the first embodiment in which Ni is precipitated in the electrolytic plating on the under bump metal 4 of the bump pattern portion opened by the photoresist process, the third embodiment of the invention precipitates Cu on an under bump metal 4 of a bump pattern portion and forms a Cu pillar 9. Further, a Ni pillar 7 is formed on the Cu pillar 9, and subsequently a photosensitive resist is removed by a stripping liquid, and the under bump metal 4 is removed by etching (not illustrated).
Since Cu is used as a plating power distribution material of the under bump metal 4 here, when the Cu under bump metal 4 is etched, the Cu pillar 9 is also etched at the same time (
Note that, in the embodiments, although explanation is made using any resist of the negative and positive resists as the photosensitive resist 5, any resist of the negative and positive resists may be used in the respective embodiments. As described above, even if any resist of the negative and positive resists is selected, a focus value in which α=90° is achieved is determined depending on the resist. Further, a tendency that a shift of a focus value in exposure from a small value to large value causes the angle between a bottom surface and a side surface of a bump shape with respect to a bump side (α of
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-212781 | Sep 2010 | JP | national |
