Patent Application
20090315163
NOT APPLICABLE
Personal electronic products, such as cell phones, personal data assistants, digital cameras, laptops, etc, are generally comprised of several packaged semiconductor IC chips and surface mount components assembled onto interconnect substrates, such as printed circuit boards and flex substrates. There is an ever increasing demand to incorporate more functionality and features into personal electronic products and the like. This, in turn, has placed ever increasing demands on the design, size, and assembly of the interconnect substrates. As the number of assembled components increases, substrate areas and costs increase, while demand for a smaller form factor increases.
As part of making their invention, the inventors have recognized that there is a need to address these issues and that it would be advantageous to find ways to enable increases in functionality and features of electronic products without causing increases in substrate areas and costs, and decreases in product yields. Also, as a part of making their inventions, the inventors have recognized that many electronic products have several components that can be grouped together in several small groups that provide specific functions. For example, an electronic product often has one or more power conversion circuits, each of which typically comprises a control IC chip, an inductor, one or two capacitors, and sometimes a resistor or two. As another example, an electronic product may have an analog-to-digital circuit and/or a digital-to-analog circuit, each of which typically comprises an IC chip, and several resistors and capacitors. Also, as part of making their invention, the inventors have discovered that the substrate area required for a circuit group can be significantly decreased by incorporating the components of the circuit group into a single package.
Accordingly, a first general embodiment of the invention is directed to a semiconductor die package broadly comprising a leadframe having a first surface, a second surface, and a plurality of conductive regions disposed between its first and second surfaces, and at least one semiconductor die disposed on the first surface of the leadframe and electrically coupled to at least one conductive region of the leadframe. The first exemplary embodiment further comprises an electrically conductive layer having a first surface, a second surface, and a plurality of conductive regions disposed between its first and second surfaces, and at least one passive electrical component disposed on the first surface of the electrically conductive layer and electrically coupled to at least one conductive region of the electrically conductive layer. The second surface of the electrically conductive layer is disposed over the first surface of the leadframe, and at least one conductive region of the electrically conductive layer is electrically coupled to at least one conductive region of the leadframe.
Another general embodiment of the invention is directed to a semiconductor die package broadly comprising an electrically conductive layer, at least one semiconductor die, and at least one passive electrical component. The electrically conductive layer has a first surface, a second surface, a thickness of less than about 0. 1 mm between its first and second surfaces, and a plurality of conductive regions disposed between its first and second surfaces. The at least one semiconductor die is disposed on the first surface of the electrically conductive layer and electrically coupled to at least one conductive region of the electrically conductive layer. The at least one passive electrical component is disposed on the second surface of the electrically conductive layer and electrically coupled to at least one conductive region of the electrically conductive layer.
Another general embodiment of the invention is directed to a method of manufacturing an electronic package broadly comprising forming a conductive layer on a first surface of a sacrificial leadframe, the conductive layer having a plurality of conductive regions, assembling at least one electrical component and the conductive layer together such that at least one electrically conductive region of the at least one electrical component is electrically coupled with a conductive region of the leadframe, disposing an electrically insulating material on at least a portion of the at least one electrical component and at least a portion of the conductive layer, and separating the conductive layer and the at least one electrical component from the sacrificial leadframe.
Another general embodiment of the invention is directed to a method of manufacturing an electronic package broadly comprising assembling at least one semiconductor die and flexible module together, the flexible module having a conductive layer and at least one passive electrical component electrically coupled to at least one electrically conductive region of the conductive layer.
The present invention also encompasses systems that include packages according to the present invention, each such system having an interconnect substrate and a semiconductor die package according to the present invention attached to the interconnect substrate, with electrical connections made therewith.
The invention enables the manufacture of ultra-miniature buck converters and other circuits to be made with board footprints as small as 2.5 mm by 2.5 mm, which can be used in portable consumer products, such as cell phones, MP3 players, PDA's, and the like.
The above general embodiments and other embodiments of the invention are described in the Detailed Description with reference to the Figures. In the Figures, like numerals may reference like elements and descriptions of some elements may not be repeated.
Regulator circuit 25 has eight (8) terminals, labeled as PVIN, SW, GND, EN, FB, and VSEL<2:0>, which are coupled to the other components of circuit group 10 as shown in
Flexible module 130 comprises a top surface 131, a bottom surface 132, an electrically conductive layer 134 disposed at bottom surface 132, and surface mount components 140, 150, and 160. Conductive layer 134 has a top surface 135, a bottom surface 136, and a plurality of conductive regions disposed therebetween, and preferably in the form of a pattern of electrical pads and traces. It has a thickness that is generally less than the thickness of a typical leadframe, being less than about 100 μm in thickness, and more generally less than about 50 μm, and typically in the range of 10 μm to 25 μm. Surface mount components 140-160 are mounted and electrically coupled to respective electrical pads of conductive layer 134 at its top surface 135. Components 140-160 may be coupled to conductive layer with bodies 138 of conductive adhesive material, such as solder.
Referring back to
A minimum footprint of package 100 is 2.5 mm by 2.5 mm, which is 31% smaller than the typical footprint of 3 mm by 3 mm needed by an optimal discrete component implementation. A typical thickness of package 100 is about 0.95 mm. While this thickness is larger than the thickness of about 0.6 mm for the discrete components, most product applications have ample vertical space and can accommodate the larger thicknesses without difficulty. Conductive region 119 comprises a leadframe die paddle onto which semiconductor die 120 is assembled, as described below in greater detail. Conductive region 119 can be thermally coupled to an external substrate, such as by solder or thermal grease, to aid in dissipating heat generated by semiconductor die 120.
The above-described construction of package 100 enables instances of flexible module 130 to be mass produced and tested separately, and thereafter assembled together with instances of leadframe 110. This enables the use of separate optimized manufacturing processes, one for surface mount components for flexible module 130 and the other for semiconductor die for leadframe 110, and the testing of components before final assembly to increase yield.
With the construction of package 100′, semiconductor die 120 and bumps 190 are each disposed on bottom surface 102, and the height of bumps 190 encompasses the height of semiconductor die 130. A typical thickness of package 100′ is about 0.9 mm, including the thickness of semiconductor die 120 (typically around 0.1 mm) and the height of bumps 190 (typically around 0.25 mm). While this thickness is larger than the thickness of about 0.6 mm for the discrete components, most product applications have ample vertical space and can accommodate the larger thicknesses without difficulty. Die 120 may be left exposed, or covered by a thin protective layer having a thickness of about 0.10 mm or less, and can be thermally coupled to an external substrate, such as by thermal grease, to aid in dissipating heat.
Package 100′ may be manufactured by assembling semiconductor die 120 and flexible module 130′ together, assembling bumps 190 and flexible module 130′ together, and optionally disposing underfill material between semiconductor die 120 and flexible module 130′. Semiconductor die 120 and flexible module 130′ may be assembled together by using gold stud flip chip bonding, which provides a low profile for die 120, or by using solder bump flip-chip bonding or other bonding methods. In one form of gold stud flip chip bonding, light pressure and ultrasonic vibrations are applied to the die to form bonds between the gold stud bumps and the conductive regions. In another form of gold stud flip chip bonding, solder paste or a polymeric conductive adhesive material (e.g., conductive epoxy) is disposed on areas of surface 136 of conductive layer 134′, such as by screen printing, the gold stud bumps are contacted with these areas, and the die and leadframe are thermally compressed together to bond the gold studs with these contacted areas of conductive layer 134′ (the heat of the thermal compression reflows the solder paste or cures the polymeric adhesive material). When using solder-bump flip-chip bonding, a solder mask may be disposed on surface 136 of conductive layer 134′ to maintain reflowing solder within the attachment areas, or, before the flip-chip bonding occurs, solder bumps may be formed on die 120 and pads of solder pads may be defined on surface 136 by screen printing. Underfill material 180 may be disposed before, during, or after the assembly of die 120 with flexible module 130′. Underfill material 180 may comprise a preformed polymer sheet with conductive bodies 125 formed therein, or a uniform preformed polymer sheet through which conductive bodies 125 are pressed, such as when die 120 is assembled with module 130′ with the bodies being first disposed on die 120. Underfill material 180 may also comprise a material that is initially in liquid form, which is disposed around the sides of an assembled die 120 and wicked into the interior of the die's top surface by capillary action. The liquid underfill material then sets to a solid phase, which may be done by heat curing or chemical action. Bumps 190 and flexible module 130′ may be assembled together before or after the assembly of module 130′ with the other components. The back surface of semiconductor die 120 may be covered by a protective material (generally less than 0.05 mm thick), or left exposed to facilitate heat conduction to a substrate to which the finished package is to be attached.
Given the above description, it should be understood that, where the performance of an action of any of the methods disclosed herein is not predicated on the completion of another action, the actions may be performed in any time sequence (e.g., time order) with respect to one another, including simultaneous performance and interleaved performance of various actions. (Interleaved performance may, for example, occur when parts of two or more actions are performed in a mixed fashion.) Accordingly, it may be appreciated that, while the method claims of the present application recite sets of actions, the method claims are not limited to the order of the actions listed in the claim language, but instead cover all of the above possible orderings, including simultaneous and interleaving performance of actions and other possible orderings not explicitly described above, unless otherwise specified by the claim language (such as by explicitly stating that one action proceeds or follows another action).
As noted above, packages 100 and 100′ provide substantial space savings over discrete component implementations. As additional advantages of the packages disclosed herein, leadframe 110 and conductive layers 134, 134′ provide reduced series resistance among the components of the circuit group, and the combination of the leadframe and/or conductive layer with insulating material 160 provides more reliable electrical connections. In addition, since the packages disclosed herein provide complete functioning circuits, the packages may be tested before being assembled onto product substrates, thereby increasing yields of the product substrates. In addition, as to power supply implementations of the packages of the present invention, the configuration of the power supply components in the packages can provide conversion efficiencies of 85% or more.
While exemplary packages 100 and 100′ have been illustrated with the use of one semiconductor die, it may be appreciated that further embodiments may include two or more semiconductor die, which may be assembled onto any surface of leadframe 110 and/or any surfaces of conductive layers 134, 134′. In addition, while the above packages have been illustrated with the passive components (140, 150, and 160) being assembled onto top surfaces 136 of conductive layers 134, 134′, further embodiments may include passive components mounted on the bottom surfaces 135 of conductive layers 134, 134′, such as ultra-thin surface mount resistors.
The semiconductor die packages described above can be used in electrical assemblies including circuit boards with the packages mounted thereon. They may also be used in systems such as phones, computers, etc.
Some of the examples described above are directed to “leadless”-type packages such as MLP-type packages (microleadframe packages) where the terminal ends of the leads do not extend past the lateral edges of the molding material. Embodiments of the invention may also include leaded packages where the leads extend past the lateral surfaces of the molding material.
Any recitation of “a”, “an”, and “the” is intended to mean one or more unless specifically indicated to the contrary.
The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described, it being recognized that various modifications are possible within the scope of the invention claimed.
Moreover, one or more features of one or more embodiments of the invention may be combined with one or more features of other embodiments of the invention without departing from the scope of the invention.
While the present invention has been particularly described with respect to the illustrated embodiments, it will be appreciated that various alterations, modifications, adaptations, and equivalent arrangements may be made based on the present disclosure, and are intended to be within the scope of the invention and the appended claims.
