This application claims priority from Korean Patent Application No. 10-2021-0101340, filed on Aug. 2, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
The exemplary embodiments of the disclosure relate to a semiconductor package including a chip connection structure.
As a result of advances in the electronics industries, electronic products are being further miniaturized and multifunctionalized. Accordingly, a semiconductor package in which a plurality of semiconductor chips are vertically stacked has been proposed. Upon stacking semiconductor chips, a metallurgical joint may be formed between a pad and a solder. In such case, failure may occur in a solder joint region due to a difference in the coefficients of thermal expansion among semiconductor chips.
The exemplary embodiments of the disclosure provide an enhancement in reliability of a solder joint region interconnecting semiconductor chips included a semiconductor package.
A semiconductor package according to an exemplary embodiment of the disclosure may include a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, and a first chip connection structure disposed between the first semiconductor chip and the second semiconductor chip. The first chip connection structure may include a first insertion connection structure connected to the first semiconductor chip, a first recess connection structure connected to the second semiconductor chip, and a first contact layer interposed between the first insertion connection structure and the first recess connection structure. The first recess connection structure may include a base and a side wall which define a recess. A portion of the first insertion connection structure may be disposed in the recess. A portion of the first contact layer may be disposed in the recess, and the first contact layer covers at least a portion of a bottom surface of the side wall.
A semiconductor package according to an exemplary embodiment of the disclosure may include a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first chip connection structure disposed between the first semiconductor chip and the second semiconductor chip, and a mold layer covering the first semiconductor chip and the second semiconductor chip. The first chip connection structure may include a first recess connection structure connected to the first semiconductor chip, a first insertion connection structure connected to the second semiconductor chip, and a first contact layer interposed between the first recess connection structure and the first insertion connection structure. The first recess connection structure may include a base and a side wall which define a recess. A portion of the first insertion connection structure may be disposed in the recess. A portion of the first contact layer may be disposed in the recess, and the first contact layer may cover at least a portion of a top surface of the side wall while being spaced apart from a bottom surface of the second semiconductor chip.
A semiconductor package according to an exemplary embodiments of the disclosure may include a base substrate, a first semiconductor chip on the base substrate, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip, a first chip connection structure between the first semiconductor chip and the second semiconductor chip, a second chip connection structure between the second semiconductor chip and the third semiconductor chip, and a mold layer disposed on the base substrate while covering the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip. One of the first chip connection structure and the second chip connection structure may include an insertion connection structure, a recess connection structure on the insertion connection structure, and a contact layer between the insertion connection structure and the recess connection structure. The first chip connection structure and the second chip connection structure may have mirror symmetry with respect to each other.
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The first to fourth semiconductor chips 100, 200, 300, and 400 may be a logic chip and/or a memory chip. For example, all of the first to fourth semiconductor chips 100, 200, 300, and 400 may be memory chips of the same kind, or a part of the first to fourth semiconductor chips 100, 200, 300, and 400 may be a memory chip, and the other part of the first to fourth semiconductor chips 100, 200, 300, and 400 may be a logic chip. The memory chip may be, for example, a volatile memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory chip such as a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In addition, the logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor. In some exemplary embodiments, each of the first to fourth semiconductor chips 100, 200, 300, and 400 may be a high bandwidth memory (HBM) DRAM.
The first semiconductor chip 100 may include a first semiconductor substrate 110, a first semiconductor element layer 120, a first through electrode 130, a first lower passivation layer 140, a lower connection structure 145, a connection terminal 147, a first upper pad 150, and a first upper passivation layer 160.
The first semiconductor substrate 110 may include silicon. Alternatively, the first semiconductor substrate 110 may include a semiconductor element such as germanium, or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) and indium phosphide (InP). Otherwise, the first semiconductor substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate 110 may include a buried oxide layer (BOX layer). The first semiconductor substrate 110 may include a conductive region, for example, a well doped with impurities, or a structure doped with impurities. In addition, the first semiconductor substrate 110 may have various element isolation structures such as a shallow trench isolation (STI) structure.
The first semiconductor substrate 110 may have a top surface and a bottom surface which are opposite to each other. The first semiconductor element layer 120 may be disposed at the side of the bottom surface of the first semiconductor substrate 110. The first semiconductor element layer 120 may include a first wiring structure 125 for connecting a plurality of individual elements to other wirings formed at the first semiconductor substrate 110. The first wiring structure 120 may include a metal wiring layer and a via plug.
The first through electrode 130 may extend through the first semiconductor substrate 110, and may extend from the top surface of the first semiconductor substrate 110 toward the bottom surface of the first semiconductor substrate 110. The first through electrode 130 may extend into the first semiconductor element layer 120. The first through electrode 130 may be connected to the first wiring structure 125 provided in the first semiconductor element layer 120, or may be directly connected to the lower connection structure 145 while extending through the first semiconductor element layer 120. The first semiconductor element layer 120 may be connected to the first upper pad 150 which is disposed on the top surface of the first semiconductor substrate 110. The through electrode 130 may have a pillar shape.
The first lower passivation layer 140 may cover a bottom surface of the first semiconductor element layer 120. For example, the first lower passivation layer 140 may be formed of an insulating layer made of photosensitive polyimide (PSPI), SiN, tetraethyl orthosilicate (TEOS), or the like.
The lower connection structure 145 may be disposed on a bottom surface of the first lower passivation layer 140. A portion of the lower connection structure 145 may be connected to the first semiconductor element layer 120 while extending through the first lower passivation layer 140. The lower connection structure 145 may be connected to the first wiring structure 125 of the first semiconductor element layer 120. For example, the lower connection structure 145 may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold.
The connection terminal 147 may be disposed on the lower connection structure 145. The connection terminal 147 may be used to electrically connect the semiconductor package 1 to an external substrate. For example, the first connection terminal 147 may include a pillar structure, a ball structure, or a solder layer. The first upper pad 150 may be disposed on the top surface of the first semiconductor substrate 110. The first upper pad 150 may include the same material as the lower connection structure 145. The first upper passivation layer 160 may be disposed on the top surface of the first semiconductor substrate 110. The first upper passivation layer 160 may cover a portion of the first upper pad 150. The first upper passivation layer 160 may include the same material as the first lower passivation layer 140, or may include a material different from that of the first lower passivation layer 140.
The second semiconductor chip 200 may be disposed on the top surface of the first semiconductor chip 100. The second semiconductor chip 200 may include a second semiconductor substrate 210, a second semiconductor element layer 220, a second through electrode 230, a second lower passivation layer 240, a second upper pad 250, and a second upper passivation layer 260.
The third semiconductor chip 300 may be disposed on the top surface of the second semiconductor chip 200. The third semiconductor chip 300 may include a third semiconductor substrate 310, a third semiconductor element layer 320, a third through electrode 330, a third lower passivation layer 340, a third upper pad 350, and a third upper passivation layer 360.
The fourth semiconductor chip 400 may be disposed on the top surface of the third semiconductor chip 300. The fourth semiconductor chip 400 may include a fourth semiconductor substrate 410, a fourth semiconductor element layer 420, and a fourth lower passivation layer 440. The fourth semiconductor chip 400 may omit a through electrode, an upper pad, and an upper passivation layer, in contrast to the other semiconductor chips.
The second to fourth semiconductor chips 200, 300 and 400 may have technical characteristics identical or similar to those of the first semiconductor chip 100 and, as such, description of the second to fourth semiconductor chips 200, 300 and 400 may be replaced by the description of the first semiconductor chip 100.
The semiconductor package 1 may include a first chip connection structure CS1, a second chip connection structure CS2, and a third chip connection structure CS3. The second semiconductor chip 200 may be mounted on the first semiconductor chip 100 via the first chip connection structure CS1. The third semiconductor chip 300 may be disposed on the second semiconductor chip 200 via the second chip connection structure CS2. The fourth semiconductor chip 400 may be disposed on the third semiconductor chip 300 via the third chip connection structure CS3.
The first chip connection structure CS1 may include a first insertion connection structure CSa, a first recess connection structure CSb, and a first contact layer SD. The first insertion connection structure CSa may be disposed on the top surface of the first semiconductor chip 100, and may be connected to the first semiconductor chip 100. The first recess connection structure CSb may be disposed on the bottom surface of the second semiconductor chip 200, and may be connected to the second semiconductor chip 200. The first recess connection structure CSb may be disposed on the first insertion connection structure CSa. The first recess connection structure CSb may be disposed to vertically overlap with the first insertion connection structure CSa corresponding thereto. At least a portion of the first contact layer SD may be interposed between the first insertion connection structure CSa and the first recess connection structure CSb. The first contact layer SD may surround an upper portion of the first insertion connection structure CSa, and may cover a portion of the first recess connection structure CSb. For example, the first insertion connection structure CSa may include at least one of nickel (Ni), gold (Au), and copper (Cu). The first recess connection structure CSb may include nickel (Ni) and/or copper (Cu). The first contact layer SD may be a solder. For example, the first contact layer SD may be a solder including tin (Sn) and at least one metal material. For example, the first contact layer SD may include at least one of SnAg, SnBi, SnCu, and SnIn.
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The first recess connection structure CSb may be disposed on the first insertion connection structure CSa, and may be spaced apart from the first insertion connection structure CSa. The first recess connection structure CSb may include a first section CSb1 and a second section CSb2. The first section CSb1 may extend into the second lower passivation layer 240. The first section CSb1 may extend through the second lower passivation layer 240 and, as such, may be connected to the second semiconductor element layer 220. For example, the first section CSb1 may be connected to a second wiring structure 225 included in the second semiconductor element layer 220.
The second section CSb2 may be disposed on the first section CSb1. The second section CSb2 may be disposed on a bottom surface of the second lower passivation layer 240. The second section CSb2 may include a base CSbb and a side wall CSbs. The base CSbb may be directly connected to the first section CSb1. A top surface of the base CSbb may contact the bottom surface of the second lower passivation layer 240. The width of the base CSbb may be greater than the width of the second section CSa2 of the first insertion connection structure CSa. The side wall CSbs may be connected to an edge of the base CSbb. The side wall CSbs may extend from the base CSbb toward the first semiconductor chip 100. The base CSbb and the side wall CSbs may define a recess R. The recess R may be defined by a bottom surface CSbbs of the base CSbb and an inner side surface CSbsi of the side wall CSbs. Each of a thickness d1 of the base CSbb and a thickness d2 of the side wall CSbs may be about 2 to 48 μm. The thickness d1 of the base CSbb and the thickness d2 of the side wall CSbs may differ from each other. A height h2 of the side wall CSbs may be 2 to 48 μm. In an exemplary embodiment, the height h2 of the side wall CSbs may be equal to or greater than the height h1 of the second section CSa2 of the first insertion connection structure CSa. The overall height d1+h2 of the second section CSb2 of the first recess connection structure CSb may be 50 μm at maximum. The side wall CSbs may be spaced apart from the first upper passivation layer 160 of the first semiconductor chip 100. A first minimum distance L1 between a bottom surface CSbse of the side wall CSbs and the first upper passivation layer 160 may be about 2 to 20 μm.
A portion of the second section CSa2 of the first insertion connection structure CSa may be disposed in the recess R of the first recess connection structure CSb. A portion of the second section CSa2 of the first insertion connection structure CSa may horizontally overlap with a portion of the side wall CSbs of the first recess connection structure CSb. The second section CSa2 of the first insertion connection structure CSa may be spaced apart from the first recess connection structure CSb by a predetermined distance, and the first insertion connection structure CSa and the first recess connection structure CSb may not directly contact each other. A second minimum distance L2 between a top surface of the first insertion connection structure CSa and a bottom surface of the base CSbb of the first recess connection structure CSb may be about 2 to 20 μm. The second minimum distance L2 may be equal to or different from the first minimum distance L1. A third minimum distance L3 between a side surface of the first insertion connection structure CSa and the inner side surface CSbsi of the first recess connection structure CSb may be about 2 to 20 μm. The third minimum distance L3 may be equal to or different from the first minimum distance L1 and/or the second minimum distance L2.
The first contact layer SD may be interposed between the first insertion connection structure CSa and the first recess connection structure CSb. A portion of the first contact layer SD may be disposed between the top surface of the first insertion connection structure CSa and the bottom surface CSbbs of the base CSbb of the first recess connection structure CSb. A portion of the first contact layer SD may be disposed between the side surface of the first insertion connection structure CSa and the inner side surface CSbsi of the first recess connection structure CSb. The first contact layer SD may contact a side surface and a top surface of the second section CSa2 of the first insertion connection structure CSa. The first contact layer SD may completely cover the side surface and the top surface of the second section CSa2 of the first insertion connection structure CSa. The first contact layer SD may contact the bottom surface CSbbs of the base CSbb, the inner side surface CSbsi of the side wall CSbs, and the bottom surface CSbse of the side wall CSbs in the first recess connection structure CSb. The first contact layer SD may completely cover the bottom surface CSbbs of the base CSbb and the inner side surface CSbsi of the side wall CSbs in the first recess connection structure CSb. The first contact layer SD may cover at least a portion of the bottom surface CSbse of the side wall CSbs of the first recess connection structure CSb. In an exemplary embodiment, the first contact layer SD may completely cover the bottom surface CSbse of the side wall CSbs of the first recess connection structure CSb. The first contact layer SD may be spaced apart from the first semiconductor chip 100. The first contact layer SD may be spaced apart from the first upper passivation layer 160. A lowermost surface SDs of the first contact layer SD may be inclined. An angle formed by the lowermost surface SDs of the first contact layer SD and the top surface of the first upper passivation layer 160 may be an acute angle. The lowermost surface SDs of the first contact layer SD may be a curved surface. The lowermost surface SDs of the first contact layer SD may interconnect the side surface of the second section CSa2 of the first insertion connection structure CSa and the bottom surface CSbse of the side wall CSbs of the first recess connection structure CSb. In an exemplary embodiment, the lowermost surface SDs of the first contact layer SD may interconnect a lower end of the side surface of the second section CSa2 of the first insertion connection structure CSa and a lower end of an outer side surface of the side wall CSbs of the first recess connection structure CSb.
The second and third chip connection structures CS2 and CS3 may have technical characteristics identical to those of the first chip connection structure CS1 and, as such, descriptions of the second and third chip connection structures CS2 and CS3 may be replaced by the description of the first chip connection structure CS1.
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The first recess connection structure CSb may further include a barrier pattern BP and a seed pattern SP. The barrier pattern BP and the seed pattern SP may constitute an upper portion of the first recess connection structure CSb. The barrier pattern BP and the seed pattern SP may extend along a top surface of the first recess connection structure CSb. The barrier pattern BP may directly contact the second lower passivation layer 240 and the second semiconductor element layer 220, and the seed pattern SP may be formed on the barrier pattern BP. For example, the barrier pattern BP may include titanium (Ti), and the seed pattern SP may include copper (Cu). Portions constituting the first recess connection structure CSb, except for the barrier pattern BP and the seed pattern SP, may be made of nickel (Ni) or copper (Cu). In an exemplary embodiment, the seed pattern SP may be omitted.
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In an exemplary embodiment, the first chip connection structure CS1a may be disposed between a first semiconductor chip 100 and a second semiconductor chip 200. Referring to
The first recess connection structure CSc may be disposed on a first upper passivation layer 160. The first recess connection structure CSc may include a first section CSc1 and a second section CSc2. The first section CSc1 may extend into the first upper passivation layer 160. The first section CSc1 may extend through the first upper passivation layer 160 and, as such, may be connected to a first upper pad 150.
The second section CSc2 may be disposed on the first section CSc1. The second section CSc2 may be disposed on a top surface of the first upper passivation layer 160. The second section CSc2 may include a base CScb and a side wall CScs. The base CScb may be directly connected to the first section CSc1. A bottom surface of the base CScb may contact the top surface of the first upper passivation layer 160. The width of the base CScb may be greater than the width of the first section CSc1. The side wall CScs may be connected to an edge of the base CScb. The side wall CScs may extend from the base CScb toward the second semiconductor chip 200. The base CScb and the side wall CScs may define a recess R. The recess R may be defined by a top surface CScbs of the base CScb and an inner side surface CScsi of the side wall CScs. The side wall CScs may be spaced apart from a second lower passivation layer 240 of the second semiconductor chip 200.
The first insertion connection structure CSd may be disposed on the first recess connection structure CSc, and may be spaced apart from the first recess connection structure CSc. The first insertion connection structure CSd may include a first section CSd1 and a second section CSd2. The first section CSd1 of the first insertion connection structure CSd may extend through the second lower passivation layer 240 and, as such, may be connected to a second semiconductor element layer 220 of the second semiconductor chip 200. The first section CSd1 of the first insertion connection structure CSd may be connected to a second wiring structure 225 of the second semiconductor element layer 220. The second section CSd2 of the first insertion connection structure CSd may be disposed under the first section cSd1, and may have a greater width than the first section CSd1. The second section CSd2 of the first insertion connection structure CSd may be disposed on a bottom surface of the second lower passivation layer 240.
A portion of the second section CSd2 of the first insertion connection structure CSd may be disposed in the recess R of the first recess connection structure CSc. A portion of the second section CSd2 of the first insertion connection structure CSd may horizontally overlap with a portion of the side wall CScs of the first recess connection structure CSc. The second section CSd2 of the first insertion connection structure CSd may be spaced apart from the first recess connection structure CSc by a predetermined distance, and the first insertion connection structure CSd and the first recess connection structure CSc may not directly contact each other.
The first contact layer SDa may be interposed between the first recess connection structure CSc and the first insertion connection structure CSd. A portion of the first contact layer SDa may be interposed between a top surface of the first insertion connection structure CSd and the top surface CScbs of the base CScb of the first recess connection structure CSc. A portion of the first contact layer SDa may be interposed between a side surface of the first insertion connection structure CSd and the inner side surface CScsi of the first recess connection structure CSc. The first contact layer SDa may contact a side surface and a top surface of the second section CSd2 of the first insertion connection structure CSd. The first contact layer SDa may completely cover the side surface and the top surface of the second section CSd2 of the first insertion connection structure CSd. The first contact layer SDa may contact the top surface CScbs of the base CScb, the inner side surface CScsi of the side wall CScs, and a top surface CScse of the side wall CScs in the first recess connection structure CSc. The first contact layer SDa may completely cover the top surface CScbs of the base CScb and the inner side surface CScsi of the side wall CScs in the first recess connection structure CSc. The first contact layer SDa may cover at least a portion of the top surface CScse of the side wall CScs of the first recess connection structure CSc. In an exemplary embodiment, the first contact layer SDa may completely cover the top surface CScse of the side wall CScs of the first recess connection structure CSc. The first contact layer SDa may be spaced apart from the second semiconductor chip 200. The first contact layer SDa may be spaced apart from the second lower passivation layer 240. An uppermost surface SDas of the first contact layer SDa may be inclined. An angle formed by the uppermost surface SDas of the first contact layer SDa and the second lower passivation layer 240 may be an acute angle. The uppermost surface SDas of the first contact layer SDa may be a curved surface. The uppermost surface SDas of the first contact layer SDa may interconnect a side surface of the second section CSd2 of the first insertion connection structure CSd and the top surface CScse of the side wall CScs of the first recess connection structure CSc. In an exemplary embodiment, the uppermost surface SDas of the first contact layer SDa may interconnect an upper end of the side surface of the second section CSd2 of the first insertion connection structure CSd and an upper end of an outer side surface of the side wall CScs of the first recess connection structure CSc.
The second chip connection structure CS2a may be disposed between the second semiconductor chip 200 and a third semiconductor chip 300, and the third chip connection structure CS3a may be disposed between the third semiconductor chip 300 and a fourth semiconductor chip 400. The second and third chip connection structures CS2a and CS3a may have technical characteristics identical to those of the first chip connection structure CS1a.
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When the base substrate 500 is an interposer, the base substrate 500 may include a substrate body 501 made of a semiconductor material, a lower pad 520, and an upper pad 510. For example, the substrate body 501 may be a silicon wafer. An inner wiring may be formed in the substrate body 501. A through via, which electrically interconnects the upper pad 510 and the lower pad 520, may be formed in the substrate body 501.
An outer connection terminal 530 may be disposed at the bottom surface of the base substrate 500. The outer connection terminal 530 may be disposed on the lower pad 520. For example, the outer connection terminal 530 may be a solder ball or a solder bump.
The upper pad 510, which is disposed at the top surface of the base substrate 500, may be connected to a connection terminal 147. A first semiconductor chip 100 may be mounted on the base substrate 500 via the connection terminal 147. The underfill material layer 540 may be interposed between the first semiconductor chip 100 and the base substrate 500 and, as such, may surround a side surface of the connection terminal 147. For example, the underfill material layer 540 may include an epoxy resin. In an exemplary embodiment, an insulating film constituted by a non-conductive film and flux may be formed between the base substrate 500 and the first semiconductor chip 100, in place of the underfill material layer 540.
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The first through electrode 130 may be formed to extend through the first semiconductor substrate 110 while extending through at least a portion of the first semiconductor element layer 120, and the first lower passivation layer 140 may be formed to cover a surface of the first semiconductor element layer 120. The lower connection structure 145 may be formed to extend through the first lower passivation layer 140, and the connection terminal 147 may be formed on the lower connection structure 145. The adhesive layer 13 may be formed to cover the connection terminal 147 and the lower connection structure 145, and the first semiconductor wafer W1 may be disposed on the carrier substrate 10 such that the adhesive layer 13, the connection terminal 147, and the lower connection structure 145 are directed to the carrier substrate 10. The first upper pad 150 and the first upper passivation layer 160 may be formed on a top surface of the first semiconductor substrate 110. After disposition of the first semiconductor wafer W1 on the carrier substrate 10, a surface directed to the carrier substrate 10 from among surfaces of the first semiconductor substrate 110 may be a bottom surface of the first semiconductor substrate 110, and a surface opposite to the bottom surface may be the top surface of the first semiconductor substrate 110.
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In
A passivation layer PA may be formed on the first surface 1s of the semiconductor wafer W1. For example, when the semiconductor element layer is disposed adjacent to the first surface 1s, the passivation layer PA may be referred to as a lower passivation layer, whereas, when the semiconductor element layer is disposed adjacent to the second surface 2s, the passivation layer PA may be referred to as an upper passivation layer.
A trench TR1 may be formed by partially etching the passivation layer PA. An upper pad (not shown) may be exposed by the trench TR1, or a top surface of the semiconductor element layer (not shown) may be exposed by the trench TR1. A barrier layer B and a seed layer S may be formed on the passivation layer PA through a sputtering process. Although the barrier layer B and the seed layer S are shown in
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A second recess connection structure CSe and a second contact layer SDb may be formed on the second upper pad 250 and the second upper passivation layer 260. The second recess connection structure CSe and the second contact layer SDb may be formed in accordance with the recess connection structure manufacturing method described with reference to
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A first insertion connection structure CSd may be formed on the second lower passivation layer 240. The first insertion connection structure CSd may extend through the second lower passivation layer 240. The first insertion connection structure CSd may be electrically connected to the second semiconductor element layer 220 and/or the second through electrode 230. The first insertion connection structure CSd may be formed in accordance with the insertion connection structure manufacturing method described with reference to
In
A passivation layer PA may be formed on the first surface 1s of the semiconductor wafer W2. For example, when the semiconductor element layer is disposed adjacent to the first surface 1s, the passivation layer PA may be referred to as a lower passivation layer, whereas, when the semiconductor element layer is disposed adjacent to the second surface 2s, the passivation layer PA may be referred to as an upper passivation layer. For example, when the first insertion connection structure CSd shown in
A trench TR2 may be formed by partially etching the passivation layer PA. A portion of the semiconductor element layer (not shown) may be exposed by the trench TR2. A barrier layer B and a seed layer S may be formed on the passivation layer PA through a sputtering process. The barrier layer B and the seed layer S may also be formed in the trench TR2. The barrier layer B may be formed on the passivation layer PA, and the seed layer S may be formed on the barrier layer B. For example, the barrier layer B may include titanium (Ti), and the seed layer S may include copper (Cu).
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In accordance with exemplary embodiments of the disclosure, it may be possible to provide a semiconductor package in which contact reliability of a chip connection structure among stacked semiconductor chips is enhanced.
While the embodiments of the disclosure have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the disclosure and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.
Number | Date | Country | Kind |
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10 2021 0101340 | Aug 2021 | KR | national |