Patent Application
20240379564
Stitching dies are used to interconnect multiple semiconductor dies to facilitate communication between the semiconductor dies.
Aspects of the disclosure are understood from the following detailed description when read with the accompanying drawings. It will be appreciated that elements and/or structures of the drawings are not necessarily be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily increased and/or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
One or more techniques for forming a semiconductor structure and resulting structures formed thereby are provided herein. According to some embodiments, the present application relates to a semiconductor structure and a method for fabricating a semiconductor structure. According to some embodiments, a stitching die interconnects multiple semiconductor dies to facilitate communication between the semiconductor dies and to allow a vertical arrangement of semiconductor dies, such as stacked dies. In some embodiments, the stitching die comprises conductive structures formed in one or more dielectric layers. The one or more dielectric layers and conductive structures are formed above a substrate layer of a semiconductor layer. The substrate layer is removed to expose one of the one or more dielectric layers. The stitching die is bonded to underlying semiconductor dies using a hybrid bonding process, and a cooling structure is formed over the exposed dielectric layer of the stitching die. The removal of the substrate layer of the stitching die allows the cooling structure to be positioned closer to the underlying semiconductor dies, thereby increasing cooling efficiency and potentially increasing processing performance.
In some embodiments, a base dielectric layer 110 is formed over the substrate layer 105. In some embodiments, the base dielectric layer 110 comprises silicon dioxide or a low-k dielectric material. In some embodiments, the base dielectric layer 110 comprises one or more layers of low-k dielectric material. Low-k dielectric materials have a k value lower than about 3.9. In some embodiments, the material for the base dielectric layer 110 comprise at least one of Si, O, C, or H, such as SiCOH, SiOC, oxygen-doped SiC (ODC), nitrogen-doped SiC (NDC), plasma-enhanced oxide (PEOX), or other suitable materials. A low-k dielectric material is, in some embodiments, further characterized or classified as ultra low-k (ULK), extra low-k (ELK), or extreme low-k (XLK), where the classification is generally based upon the k value. For example, ULK generally refers to materials with a k value of between about 2.7 to about 2.4, ELK generally refers to materials with a k value of between about 2.3 to about 2.0, and XLK generally refers to materials with a k value of less than about 2.0. Organic material, such as polymers, may be used for the base dielectric layer 110. In some embodiments, the base dielectric layer 110 comprises one or more layers of a carbon-containing material, organo-silicate glass, a porogen-containing material, or combinations thereof. The base dielectric layer 110 comprises nitrogen in some embodiments. In some embodiments, the base dielectric layer 110 is formed by using, for example, at least one of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), a spin-on technology, or some other suitable process.
In some embodiments, the semiconductor stitching structure 100 comprises one or more interlayer dielectric layers 115 formed over the base dielectric layer 110. According to some embodiments, the one or more interlayer dielectric layers 115 comprise a first interlayer dielectric layer 115A, a second interlayer dielectric layer 115B, and an N-th interlayer dielectric layer 115N. Any number of interlayer dielectric layers 115 are contemplated. One of the interlayer dielectric layers 115 may comprise a standard dielectric material with a medium or low dielectric constant, such as SiO2. In some embodiments, at least one of the interlayer dielectric layers 115 comprises a dielectric material with a relatively low dielectric constant, as described for the base dielectric layer 110. The interlayer dielectric layers 115 are formed in any number of ways, such as by thermal growth, chemical growth, atomic layer deposition (ALD), CVD, PECVD, or some other suitable process. In some embodiments, one or more of the interlayer dielectric layers 115 in a lower portion comprise ULK or ELK dielectric materials, one or more of the interlayer dielectric layers 115 in an intermediate portion comprise low-k dielectric materials, and one or more of the interlayer dielectric layers 115 in an upper portion comprise standard-k dielectric materials, such as doped or undoped silicon glass.
In some embodiments, the semiconductor stitching structure 100 comprises one or more etch stop layers 120 separating the interlayer dielectric layers 115. In some embodiments, the etch stop layers 120 stop an etching process between the interlayer dielectric layers 115. According to some embodiments, the etch stop layers 120 comprise a dielectric material having a different etch selectivity from the interlayer dielectric layers 115. In some embodiments, at least one of the etch stop layers 120 comprises SiN, SiCN, SiCO, CN, etc., alone or in combination. The etch stop layers 120 are formed in any number of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process.
In some embodiments, the semiconductor stitching structure 100 comprises one or more conductive contacts 125A, 125B, 125C, 125D formed in the interlayer dielectric layer 115A. The conductive contacts 125A, 125B, 125C, 125D are formed in any number of ways, such as by a single damascene process, a dual damascene process, a trench silicide process, or some other suitable process. In some embodiments, the conductive contacts 125A, 125B, 125C, 125D comprise a barrier layer, a seed layer, a metal fill layer, or other suitable layers. The metal fill layer may comprise tungsten, aluminum, copper, cobalt, or other suitable material. Other structures and configurations of the conductive contacts 125A, 125B, 125C, 125D are within the scope of the present disclosure.
In some embodiments, the semiconductor stitching structure 100 comprises one or more conductive contacts 130A, 130B, 130C, 130D formed in the interlayer dielectric layer 115B. In some embodiments, the conductive contacts 130A, 130B, 130C, 130D extend through the interlayer dielectric layer 115B. In some embodiments, some of the conductive contacts 130A, 130B, 130C, 130D comprise a via portion 130V and a line portion 130L. The line portions 130L have an axial length extending into the page. In some embodiments, the conductive contacts 130A, 130B, 130C, 130D comprise a barrier layer, a seed layer, a metal fill layer, or other suitable layers. The metal fill layer may comprise tungsten, aluminum, copper, cobalt, or other suitable material. Other structures and configurations of the conductive contacts 130A, 130B, 130C, 130D are within the scope of the present disclosure.
In some embodiments, the semiconductor stitching structure 100 comprises one or more conductive contacts 135A, 135B, 135C, 135D formed in the interlayer dielectric layer 115N. In some embodiments, the conductive contacts 135A, 135B, 135C, 135D extend through the interlayer dielectric layer 115N. Some of the conductive contacts 135A, 135B, 135C, 135D may comprise via portions 135V and a line portion 135L. The line portions 135L have an axial length extending into the page. In some embodiments, the conductive contacts 135A, 135B, 135C, 135D comprise a barrier layer, a seed layer, a metal fill layer, or other suitable layers. The metal fill layer may comprise tungsten, aluminum, copper, cobalt, or other suitable material. Other structures and configurations of the conductive contacts 135A, 135B, 135C, 135D are within the scope of the present disclosure.
The conductive contacts 125A, 130A, 135A define a seal ring for the semiconductor stitching structure 100. The conductive contacts 125B, 130B, 135B and the conductive contacts 125D, 130D, 135D define conductive structures with external contacts, and the conductive contacts 125C, 130C, 135C define a conductive structure without an external contact.
In some embodiments, a passivation layer 140 is formed over the uppermost interlayer dielectric layer 115N. The passivation layer 140 may comprise one or more layers. In some embodiments, the passivation layer 140 comprises a polymer layer such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), an inorganic-organic hybrid material, such as ORMOCER®, or some other suitable passivation material. The passivation layer 140 serves as a mechanical protection and stress buffer layer. In some embodiments, a precursor of the passivation layer 140 is deposited by spin coating and/or other suitable techniques. Conductive contact pads 145A, 145B are formed in the passivation layer 140 to contact underling the conductive contacts 135A, 135C, respectively. In some embodiments, the conductive contact pads 145A, 145B comprise a barrier layer, a seed layer, a metal fill layer, or other suitable layers. The metal fill layer may comprise tungsten, aluminum, copper, cobalt, or other suitable material. The conductive contact pads 145A, 145B may be formed by forming recesses in the passivation layer 140, forming the material of the conductive contact pads 145A, 145B in the recesses, and performing a planarization process to remove portions of the material outside the recesses.
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According to some embodiments, the semiconductor structure 200 comprises a first device 210A and a second device 210B formed on or within the substrate layer 205. In some embodiments, the first device 210A and the second device 210B cach comprises a gate dielectric layer 215A, 215B, a gate electrode 220A, 220B, source/drain regions 225A, 225B, a sidewall spacer 230A, 230B, a gate cap layer 235A, 235B, etc. According to some embodiments, the gate dielectric layer 215A, 215B and the gate electrode 220A, 220B are formed using a gate replacement process. A sacrificial gate structure comprising a sacrificial gate dielectric layer, a sacrificial gate electrode layer, such as a polysilicon layer, and a hard mask layer are formed. In some embodiments, a patterning process is performed to pattern the hard mask layer corresponding to a pattern of gate structures to be formed, and an etch process is performed using the patterned hard mask layer to etch the sacrificial gate electrode layer and the sacrificial gate dielectric layer to define the sacrificial gate structure. In some embodiments, remaining portions of the hard mask layer form a cap layer over the portions of the sacrificial gate electrode layer remaining after the etch process. The sacrificial gate structure is later replaced with a replacement gate dielectric layer, such as the gate dielectric layer 215A, 215B and a replacement gate electrode, such as the gate electrode 220A, 220B.
In some embodiments, the gate dielectric layer 215A, 215B comprises a high-k dielectric material. As used herein, the term “high-k dielectric” refers to the material having a dielectric constant, k, greater than or equal to about 3.9, which is the k value of SiO2. The high-k dielectric material may be any suitable material. Examples of the high-k dielectric material include but are not limited to Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, AL2OxNy, HfOxNy, ZrOxNy, La2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2. In some embodiments, the gate electrode 220A, 220B comprises a barrier layer, one or more work function material layers, a seed layer, a metal fill layer, or other suitable layers. In some embodiments, the metal fill layer comprises tungsten, aluminum, copper, cobalt, or other suitable material. In some embodiments, the gate dielectric layer 215A, 215B and the one or more layers that comprise the gate electrode 220A, 220B are deposited by at least one of ALD, physical vapor deposition (PVD), CVD, LPCVD, ALCVD, ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), or other suitable techniques. In some embodiments, the gate electrode 220A, 220B is recessed and the gate cap layer 235A, 235B is formed in the recess.
In some embodiments, the sidewall spacer 230A, 230B is formed adjacent the gate dielectric layer 215A, 215B and the gate electrode 220A, 220B. In some embodiments, the sidewall spacer 230A, 230B is formed by depositing a spacer layer over the sacrificial gate structure and performing an anisotropic etch process to remove horizontal portions of the spacer layer. In some embodiments, the sidewall spacer 230A, 230B comprises silicon nitride or other suitable materials.
In some embodiments, the source/drain regions 225A, 225B are formed in the substrate layer 205 after forming the sacrificial gate structure. For example, in some embodiments, portions of the substrate layer 205 are doped through an implantation process to form the source/drain regions 225A, 225B. In some embodiments, an etch process is performed to recess the substrate layer 205 adjacent the sidewall spacer 230A, 230B, and an epitaxial growth process is performed to form the source/drain regions 225A, 225B.
In an embodiment, one or more shallow trench isolation (STI) structures 240 are formed within the substrate layer 205. In some embodiments, the STI structures 240 are formed by forming at least one mask layer over the substrate layer 205. In some embodiments, the at least one mask layer comprises a layer of oxide material over the substrate layer 205 and a layer of nitride material over the layer of oxide material, and/or one or more other suitable layers. At least some of the at least one mask layer is removed to define an etch mask for use as a template to etch the substrate layer 205 to form trenches. A dielectric material is formed in the trenches to define the STI structure 240. In some embodiments, the STI structures 240 include multiple layers, such as an oxide liner, a nitride liner formed over the oxide liner, an oxide fill material formed over the nitride liner, and/or other suitable materials. Other structures and/or configurations of the STI structures 240 are within the scope of the present disclosure.
In some embodiments, the devices 210A, 210B are formed using the same materials and layer thicknesses. In some embodiments, different materials and/or thicknesses may be used due to the different voltage domains. For example, the material and/or thickness of the gate dielectric layers 215A, 215B may differ from one another. In some embodiments, the materials of the gate electrode 220A, 220B may also differ. Other structures and configurations of the devices 210A, 210B are within the scope of the present disclosure. For example, the devices 210A, 210B may be fin field-effect transistor (finFET) devices, nanosheet devices, nanowire devices, or some other suitable device.
In some embodiments, a dielectric layer 245 is formed over the devices 210A, 210B. In some embodiments, the dielectric layer 245 comprises silicon dioxide or a low-k dielectric material. In some embodiments, the dielectric layer 245 is formed by using, for example, at least one of CVD, PECVD, LPCVD, ALCVD, a spin-on technology, or some other suitable process.
In some embodiments, the semiconductor structure 200 comprises one or more conductive contacts 250A, 250B formed in the dielectric layer 245. The conductive contacts 250A, 250B are formed in any number of ways, such as by a single damascene process, a dual damascene process, a trench silicide process, or some other suitable process. In some embodiments, the conductive contacts 250A, 250B contact the gate electrodes 220A, 220B, and additional contacts (not shown) are formed to contact the source/drain regions 225A, 225B in different positions along the axial lengths of the devices 210A, 210B such as into or out of the page. In some embodiments, the conductive contacts 250A, 250B comprise a barrier layer, a seed layer, a metal fill layer, or other suitable layers. In some embodiments, the metal fill layer comprises tungsten, aluminum, copper, cobalt, or other suitable material. In some embodiments, the devices 210A, 210B, the conductive contacts 250A, 250B, and the dielectric layer 245 define a device layer 255 of the semiconductor structure 200. Other structures and configurations of the conductive contacts 250A, 250B are within the scope of the present disclosure.
In some embodiments, the semiconductor structure 200 comprises one or more dielectric layers 260 formed over the device layer 255. According to some embodiments, the one or more dielectric layers 260 comprise a second dielectric layer 260A, a third dielectric layer 260B, a fourth dielectric layer 260C, and an n-th dielectric layer 260N. Any number of dielectric layers 260 are contemplated. In some embodiments, at least one of the dielectric layers 260 comprises a standard dielectric material with a medium or low dielectric constant, such as SiO2. In some embodiments, at least one of the dielectric layers 260 comprises a dielectric material with a relatively low dielectric constant, as described for the dielectric layer 245. The dielectric layers 260 are formed in any number of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process. In some embodiments, one or more of the dielectric layers 260 in a lower portion comprise ULK or ELK dielectric materials, one or more of the dielectric layers 260 in an intermediate portion comprise low-k dielectric materials, and one or more of the dielectric layers 260 in an upper portion comprise standard-k dielectric materials, such as doped or undoped silicon glass.
In some embodiments, the semiconductor structure 200 comprises one or more etch stop layers 265 separating the dielectric layers 260. In some embodiments, the etch stop layers 265 stop an etching process between the dielectric layers 260. According to some embodiments, the etch stop layers 265 comprise a dielectric material having a different etch selectivity from the dielectric layers 260. In some embodiments, at least one of the etch stop layers 265 comprises SiN, SiCN, SiCO, CN, etc., alone or in combination. The etch stop layers 265 are formed in any number of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process.
In some embodiments, the semiconductor structure 200 comprises one or more conductive structures 270A, 270B, 270C, 270D. The conductive structures 270A, 270B, 270C, 270D may be formed using similar techniques described above in reference to
In some embodiments, a passivation layer 275 is formed over the uppermost dielectric layer 260N. The passivation layer 275 may comprise one or more layers. In some embodiments, the passivation layer 275 comprises a polymer layer such as polyimide, BCB, PBO, an inorganic-organic hybrid material, such as ORMOCER®, or some other suitable passivation material. The passivation layer 275 serves as a mechanical protection and stress buffer layer. In some embodiments, a precursor of the passivation layer 275 is deposited by spin coating and/or other suitable techniques. Conductive contact pads 280A, 280B are formed in the passivation layer 275 to contact underling the conductive structures 270A, 270B, respectively. In some embodiments, the conductive contact pads 280A, 280B comprise a barrier layer, a seed layer, a metal fill layer, or other suitable layers. The metal fill layer may comprise tungsten, aluminum, copper, cobalt, or other suitable material. The conductive contact pads 280A, 280B may be formed by forming recesses in the passivation layer 275, forming the material of the conductive contact pads 280A, 280B in the recesses, and performing a planarization process to remove portions of the material outside the recesses. A semiconductor wafer comprising a plurality of semiconductor structures 200 may be cut to provide a semiconductor die 285 having a top surface 290 and a back surface 295.
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The stitching die 170 facilitates communication between semiconductor dies 285 and die stacking to provide a combined processing complex that has a reduced footprint compared to a single semiconductor die with the same number of functional devices. The removal of the substrate layer 105 of the stitching die 170 allows the cooling structure 345, 445 to be positioned closer to the underlying semiconductor dies 285, thereby increasing cooling efficiency and potentially increasing processing performance.
In some embodiments, an apparatus includes a first semiconductor die including a first contact pad, a second semiconductor die including a second contact pad, a stitching die over the first semiconductor die and the second semiconductor die and including a third contact pad connected to the first contact pad and a fourth contact pad connected to the second contact pad. The apparatus also includes a cooling structure over the stitching die. The stitching die includes a first surface comprises a first dielectric material directly contacting the cooling structure.
In some embodiments, a method includes forming a stitching die by forming a dielectric layer over a first substrate layer, forming a first conductive structure in the dielectric layer and extending to a first surface of the dielectric layer, forming a second conductive structure in the dielectric layer and extending to the first surface of the dielectric layer, and removing the first substrate layer to expose a second surface of the dielectric layer. The stitching die is bonded to a first semiconductor die including a third conductive structure and to a second semiconductor die including a fourth conductive structure. The first conductive structure contacts the third conductive structure and the second conductive structure contacts the fourth conductive structure.
In some embodiments, a stitching die includes a dielectric layer having a first exposed surface and a second exposed surface, a first conductive structure embedded in the dielectric layer and extending to the first exposed surface without extending to the second exposed surface, and a second conductive structure embedded in the dielectric layer and extending to the first exposed surface without extending to the second exposed surface.
The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand various aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of various embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.
Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed to imply that these operations are necessarily order dependent. Alternative ordering will be appreciated having the benefit of this description. Further, it will be understood that not all operations are necessarily present in each embodiment provided herein. Also, it will be understood that not all operations are necessary in some embodiments.
It will be appreciated that layers, features, elements, etc., depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD), for example.
Moreover, “exemplary” is used herein to mean serving as an example, instance, illustration, etc., and not necessarily as advantageous. As used in this application, “or” is intended to mean an inclusive “or” rather than an exclusive “or”. In addition, “a” and “an” as used in this application and the appended claims are generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Also, at least one of A and B and/or the like generally means A or B or both A and B. Furthermore, to the extent that “includes”, “having”, “has”, “with”, or variants thereof are used, such terms are intended to be inclusive in a manner similar to the term “comprising”. Also, unless specified otherwise, “first,” “second,” or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or the same element.
Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others of ordinary skill in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure comprises all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.
