Patent Application
20140252561
This application relates to integrated circuit packaging, and more particularly to a package-on-package (PoP) structure in which the bottom package includes through substrate vias (TSVs).
Package-on-package (PoP) structures have been developed for applications such as cellular telephones and other portable devices in which circuit board space must be conserved. The top package is typically a memory package whereas the bottom package is generally a processor package. PoP technology has proven to be quite popular as compared to other approaches such a stacked-die circuit. For example, a manufacturer can readily substitute different memory packages in a PoP circuit as opposed to being tied to a particular memory, which lowers costs. Moreover, the top and bottom packages may be tested independently. In contrast, a bad die in a stacked-die design requires rejection of the remaining good die.
Although the packaging of integrated circuits using PoP structures is quite popular, challenges remain in this packaging process such as reducing the interconnect pitch between the top package and the bottom package. As technology advances, the bus width between the top package and the bottom package increases accordingly. But the ball pitch or through molded via pitch between the top substrate and the bottom substrate can only accommodate a certain number of signals. To address the small-pitch requirements, a molded-embedded PoP (MEP) has been developed. In an MEP, an additional substrate may be included between the top and bottom packages. For example,
Accordingly, there is a need in the art for improved PoP architectures to provide increased density.
A via-enabled package-on-package (PoP) circuit includes a first package die having a plurality of through substrate vias (TSVs). The TSVs are configured to carry the input/output signaling for at least one second package die in an adjoining second package. As used herein, “input/output signaling” includes all the electrical signals received by the second package die(s), including power and ground. Similarly, “input/output signaling” includes all output signals from the second package die(s).
Since the TSVs in the first package die carry the input/output signaling for the second package dies(s), no through mold via pillars or solder ball interconnects between the second package substrate and the first package substrate are needed to accommodate the input/output signaling. This is quite advantageous because the first package substrate may then be sized to just accommodate the first package die. In contrast, a conventional PoP bottom package substrate requires a substantial unoccupied first package substrate area to accommodate the interconnects to the second package substrate.
Although the first package die may include a backside redistribution layer to increase routing options for the input/output signaling to the second package, a TSV-containing interposer may also be arranged between the second package substrate and the first package die to aid in the redistribution of the input/output signaling. The interposer may be passive or may include active devices analogous to those in the first package die. Regardless of whether an interposer is included, the resulting TSV-enabled PoP (TEP) can advantageously accommodate a large number of input/output signals to the top package because of the high pitch density for TSVs across the surface area of the bottom package die.
To address the need in the art to accommodate the increasing number of input and output signals for the top packages die (or dies), an improved package-on-package (PoP) structure is provided that does not suffer from the package-to-package interconnect limitations of conventional PoPs.
In the improved PoP disclosed herein, the first package die includes a plurality of through substrate vias (TSVs) to accommodate the input and output signaling needs of a second package die (or dies). The whole area of the first package die can thus be used for the interconnects to the second package. In contrast, a conventional PoP such as MEP 100 of
To avoid any ambiguity as to what is a “top” vs “bottom” package, the bottom package for the improved PoP architectures disclosed herein is referred as a first package. Similarly, the top package is referred to as a second package. The improved PoP architectures disclosed herein can accommodate a substantially higher number of I/O signals for the second package die because the first package die area is then available to accommodate the I/O signals through its TSVs. In addition, the first package substrate size may be reduced as no substantial surface area for the first package substrate is necessary outside the surface area necessary to accommodate the footprint of the first package die. In contrast, conventional PoPs require an annular outer region on the first package substrate outside of the first package die footprint to have a sufficient size to accommodate the package-to-package interconnects. The resulting increased size of the first package substrate increases the likelihood of warping for conventional PoPs. But the improved PoPs disclosed herein advantageously can reduce warpage through the reduced size of the first package substrate. Moreover, the mold through vias or other techniques used to form conventional package-to-package interconnects are unnecessary for the improved PoPs disclosed.
The following discussion will assume without loss of generality that the first package die is a silicon die such that the through substrate vias it contains are through silicon vias. But it will be appreciated that the packaging concepts and architectures disclosed herein are widely applicable to other types of semiconductor dies. As known in the packaging arts, the process used to construct stacked devices using through silicon vias is known as a through silicon stacking (TSS) process. The resulting improved PoP disclosed herein is thus denoted as a TSS-enabled PoP (TEP). A TEP may include an interposer to provide enhanced redistribution of the input/output (I/O) signaling between its first and second packages. Alternatively, a TEP may have the first and second packages coupled together through interconnects without the user of an interposer. An interposer-containing embodiment will be discussed first followed by discussion of a directly-coupled embodiment (no interposer).
The terms “first package” and “second package” are used herein simply to denote the different packages as is known in the PoP arts. In that regard, first package 316 of
Because virtually the entire area of first package die 310 may be used for through silicon vias 322, the interconnect restrictions in PoP technology with regard to the second package die I/O are avoided. In contrast, prior art PoP architectures require the interconnects between the top package substrate and the bottom package substrate to avoid the substrate area on the bottom package substrate occupied by the bottom package die such as discussed above with regard to MEP 100. Prior-art PoP architectures thus have limited signal density as compared to the improved PoPs disclosed herein because the package-to-package interconnects are not limited to a placement on the peripheral of the bottom package substrate.
TEP 300 includes an interposer 305 having through substrate vias (TSVs) 321 that couple to through silicon vias 322 in first package die 310 through corresponding interconnects such as micro-bumps 323. Interposer 305 may comprise a semiconductor substrate such as silicon, glass, or other suitable materials. Should interposer 305 comprise a silicon substrate, TSVs 321 are through silicon vias. On the other hand, should interposer 305 comprise glass, TSVs 332 are through glass vias (TGVs). The following discussion will assume without loss of generality that TSVs 321 are through silicon vias.
Interposer 305 allows for additional redistribution of the I/O signaling to second package dies 324. Alternatively, through silicon vias 321 in interposer 305 may couple to the first package die's through silicon vias 322 through a backside redistribution layer (not illustrated) on the backside of first package die 310. Pads (not illustrated) on a lower surface of second package substrate 320 couple to the interposer through silicon vias 321 through interconnects such as bumps 325. More generally, second package substrate 320 may be considered to have a first surface and an opposing second surface. Second package dies 324 are mounted on the first surface of second package substrate 320 whereas bumps 325 connect to the opposing second surface of second package substrate 320.
In TEP 300, second package dies 324 are wire-bonded to second package substrate 320 although other mounting technologies may be used such as surface mounting. The wire bonds carry the I/O signaling between second package dies 324 and second package substrate 320. In turn, the I/O signaling for second package dies 324 is carried between second package substrate 320 and interposer 305 through bumps 325. Finally, the I/O signaling for second package dies 324 is carried between interposer 305 and first package die 310 through interposer through silicon vias 321 and first package die's through silicon vias 322. Some I/O signaling for second package dies 324 may originate from or be transmitted to external devices. Such external device I/O would be carried between interposer 305 and the external devices through though silicon vias 322 in first package die 310, bumps 309, first package substrate 360 and balls 361 on a lower surface of first package substrate 360. Interposer 305 may include active devices and/or passive components in some embodiments.
As used herein, “bump” is used to denote a structure such as a solder ball or bump. In addition, this term will be understood to also include structures such as copper pillars. In that regard, bumps 325 refer generically to the interconnecting structures that couple from pads on a bottom surface of second package substrate 320 to through silicon vias 321 on interposer 305.
Regardless of whether an interposer is included or not, bumps 325 are not restricted to an annular region outside of the area occupied by first package die 310 in direct contrast to conventional PoPs such as MEP 100.
The manufacture of a first package for an interposer-containing TEP embodiment will now be discussed with regard to
A through-silicon-via-fabricated interposer 600 may then be bonded to a back surface 605 of first package die 500 as shown in
Mold compound 715 may then be applied to complete a TEP first package 700 as shown in
As discussed above, for TEP embodiments that include an interposer, the interposer may be passive or contain active elements. In that regard, an active interposer comprises another die comparable to the first package die discussed above. Several such TSV-containing dies could be stacked within the first package. Moreover, multiple interposers may be used in parallel as shown for TEP 900 of
Referring again to first package die 310, first package die 310 may be considered to include a means for carrying the input/output signaling for at least one second package die. In one embodiment, such a means comprises TSVs 322. In an alternative embodiment, the means may comprise deep diffusion regions that couple between pads on a back surface of first package die 310 and active circuitry on an active front surface for first package die 310.
It will be appreciated that the TEP structures disclosed herein may be incorporated into a wide variety of electronic systems. For example, as shown in
As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the spirit and scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
