Circuit board and package structure thereof

Abstract

A circuit board and a package structure thereof are proposed. The circuit board includes a main body and a solder mask layer covered on a surface of the main body. The circuit board is formed with a cutting path to define a plurality of array-arranged circuit board units, wherein the solder mask layer is formed with a groove at a position corresponding to the cutting path to expose the main body of the circuit board. By such arrangement, when a laser is employed to perform a singulation process after a chip mounting process and a packaging process have been completed on the circuit board unit, the problem wherein the solder mask layer melts on the cutting path of the circuit board due to a thermal effect caused by the laser is avoided, so as to avoid the generation of irregular and uneven surface of the cutting plane. Additionally, chippings on a surface of a substrate can be prevented from being generated, so as to avoid contamination of subsequent processes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:

FIG. 1A and FIG. 1B are top-view and side-view diagrams showing a prior-art thin and fine ball grid array (TFBGA) package;

FIG. 2A and FIG. 2B are, respectively, an overall top-view diagram of an array-arranged circuit board and a detailed cutaway side-view of an individual circuit board unit of the array-arranged circuit board shown in FIG. 2A depicting fabrication of a memory card according to Taiwan Patent No. 217280;

FIG. 3A is a bottom view of a circuit board according to the first preferred embodiment of the present invention;

FIG. 3B is a cross-sectional view of a circuit board according to the first preferred embodiment of the present invention;

FIG. 4A and FIG. 4B are, respectively, a cross-sectional view and a bottom view of a circuit board unit formed by performing a singulation process to the array-arranged circuit board shown in FIG. 3A and FIG. 3B;

FIG. 5 is a cross-sectional view of a semiconductor package structure according to the present invention;

FIG. 6 is a close-up view showing the package structure produced by performing a singulation process to the semiconductor package structure shown in FIG. 5 along a cutting path surrounding each circuit board unit;

FIG. 7 is a cross-sectional view of a circuit board according to the second preferred embodiment of the present invention; and

FIG. 8 is a bottom view of a circuit board according to the third preferred embodiment of the present invention.

Claims

1. A circuit board formed with a cutting path for defining a plurality of array-arranged circuit board units, comprising: a main body; anda solder mask layer covered on a surface of the main body, wherein the solder mask layer is formed with a groove at a position corresponding to the cutting path, so as to expose the main body.

2. The circuit board of claim 1, wherein the main body comprises at least an insulating core layer and at least a patterned circuit layer built on the insulating core layer.

3. The circuit board of claim 2, wherein the groove serves to expose the insulating core layer.

4. The circuit board of claim 1, wherein the width of the groove is greater than the cutting width of the cutting path.

5. The circuit board of claim 1, wherein the circuit board can be formed with a plurality of circuit board units after a singulation process is performed along the cutting path, the circuit board units comprising a main body and a solder mask layer covered on a surface of the main body, wherein the plane size of the solder mask layer is smaller than that of the main body of the circuit board unit, so as to expose an edge of the main body of the circuit board unit.

6. The circuit board of claim 1, wherein the circuit board can be a package substrate applied to a ball grid array (BGA) semiconductor package, a package substrate applied to a thin and fine ball grid array (TFBGA) package, or a circuit board applied to a card-type package.

7. The circuit board of claim 1, wherein the solder mask layer is formed with an opening to expose an electrical pad formed on the circuit board for external electrical connection.

8. The circuit board of claim 1, wherein the groove of the solder mask layer is formed on an upper surface and a lower surface of the main body.

9. The circuit board of claim 1, wherein the groove of the solder mask layer is formed on a single surface of the main body.

10. The circuit board of claim 1, wherein a laser is applied to perform a singulation process on the circuit board.

11. The circuit board of claim 1, wherein an non-linear cutting path is formed on the circuit board.

12. A semiconductor package structure, comprising of: a circuit board comprising a main body and a solder mask layer covered on a surface of the main body, the circuit board being formed with a cutting path for defining a plurality of array-arranged circuit board units, wherein the solder mask layer is formed with a groove at a position corresponding to the cutting path to expose the main body;a semiconductor chip mounted and electrically connected to each of the circuit board units; andan encapsulant formed on the circuit board for encapsulating the semiconductor chip.

13. The semiconductor package structure of claim 12, wherein the main body comprises at least an insulating core layer and at least a patterned circuit layer built on the insulating core layer.

14. The semiconductor package structure of claim 13, wherein the groove serves to expose the insulating core layer.

15. The semiconductor package structure of claim 12, wherein the width of the groove is greater than the cutting width of the cutting path.

16. The semiconductor package structure of claim 12, wherein the package structure can be formed with a plurality of package units by performing a singulation process along the cutting path, the package units comprising: a circuit board unit comprising a main body and a solder mask layer covered on a surface of the main body, wherein the plane size of the solder mask layer is smaller than that of the main body of the circuit board unit, so as to expose an edge of the main body of the circuit board unit;a semiconductor chip mounted and electrically connected to the circuit board unit; andan encapsulant formed on the circuit board unit for encapsulating the semiconductor chip.

17. The semiconductor package structure of claim 12, wherein the circuit board can be a package substrate applied to a ball grid array (BGA) semiconductor package, a package substrate applied to a thin and fine ball grid array (TFBGA) package, or a circuit board applied to a card-type package.

18. The semiconductor package structure of claim 12, wherein the solder mask layer is formed with an opening to expose an electrical pad formed on the circuit board for external electrical connection.

19. The semiconductor package structure of claim 12, wherein the groove of the solder mask layer is formed on an upper surface and a lower surface of the main body.

20. The semiconductor package structure of claim 12, wherein the groove of the solder mask layer is formed on a single surface of the main body.

21. The semiconductor package structure of claim 12, wherein a laser is employed to perform a singulation process on the circuit board.

22. The semiconductor package structure of claim 12, wherein an non-linear cutting path is formed on the circuit board.