Circuit board structure embedded with semiconductor chips

Abstract

A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Description

BRIEF DESCRIPTION OF DRAWINGS

The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:

FIG. 1 is a cross sectional view of a package member having a substrate embedded with semiconductor chips according to the prior art;

FIG. 2 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a first embodiment according to the present invention;

FIG. 3 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a second embodiment according to the present invention;

FIG. 4 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a third embodiment according to the present invention;

FIG. 5 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fourth embodiment according to the present invention;

FIG. 6 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fifth embodiment according to the present invention; and

FIG. 7 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a sixth embodiment according to the present invention.

Claims

1. A circuit board structure embedded with semiconductor chips, the circuit board structure comprising: a supporting board having at least a cavity;at least a semiconductor chip embedded in the cavity of the supporting board, the semiconductor chip having an active surface having a plurality of the electrode pads;a protection layer formed on the active surface of the semiconductor chip, the protection layer having a plurality of openings corresponding to the electrode pads for exposure of the electrode pads of the semiconductor chip;a metal layer formed on surfaces of the electrode pads exposed from the openings of the protection layer;a dielectric layer formed on the supporting board and the protection layer surface, the dielectric layer having another plurality of openings corresponding to the electrode pads for exposure of the metal layer on the electrode pads of the semiconductor chip; anda circuit layer formed on the dielectric layer, a plurality of hollow conductive vias being formed in the another openings of the dielectric layer and electrically connected to the circuit layer, allowing the circuit layer to be electrically connected via the hollow conductive vias to the metal layer on the electrode pads of the semiconductor chip.

2. The circuit board structure of claim 1, wherein supporting board is a circuit board or a core board, which the circuit board has completed a former circuit manufacturing process.

3. The circuit board structure of claim 2, wherein the core board is made of metal or nonmetal materials.

4. The circuit board structure of claim 1 further comprising a buffer metal layer formed between the metal layer and the hollow conductive vias.

5. The circuit board structure of claim 4 further comprising a circuit build-up structure formed on the dielectric layer and the circuit layer, a plurality of fully-plated metal vias being formed in the circuit build-up structure and electrically connected to the circuit layer, an electrical conductive pad being formed on the circuit build-up structure.

6. The circuit board structure of claim 5 further comprising a solder mask formed on an external surface of the circuit build-up structure, the solder mask having a mask opening for exposure of the electrical conductive pad of the circuit build-up structure.

7. The circuit board structure of claim 5, wherein the circuit build-up structure comprises at least a dielectric layer, a circuit layer stacked on the dielectric layer, and a fully-plated metal via formed in the dielectric layer.

8. The circuit board structure of claim 5, wherein the fully-plated metal via is extended to a bottom portion of the hollow conductive vias of the circuit layer.

9. The circuit board structure of claim 1 further comprising a circuit build-up structure formed on the dielectric layer and the circuit layer, a plurality of fully-plated metal vias being formed in the circuit build-up structure and electrically connected to the circuit layer, an electrical conductive pad being formed on the circuit build-up structure.

10. The circuit board structure of claim 9 further comprising a solder mask formed on an external surface of the circuit build-up structure, the solder mask having a mask opening for exposure of the electrical conductive pad of the circuit build-up structure.

11. The circuit board structure of claim 9, wherein the circuit build-up structure comprises at least a dielectric layer, a circuit layer stacked on the dielectric layer, and a fully-plated metal via formed in the dielectric layer.

12. The circuit board structure of claim 9, wherein the fully-plated metal via is extended to a bottom portion of the hollow conductive vias of the circuit layer.