The present invention relates generally to fabrication of semiconductor chip interconnection, and more specifically to bump fabrication.
In a growing market demand to improve existing semiconductor device performance on power devices, that is devices that consume a lot of energy such as amplifiers.
Current round or round-like (such as hexagonal or octagonal) solder bump interconnects have become a bottleneck to improve electrical performance to address current flow to the chip level and heat dissipation capability down to the PCB. For example, the “Advanced Connections,” Spring 2002, Advanced Interconnect Technologies, issue describes, inter alia, a pillar bumping interconnect technology that uses perimeter or array flip-chip pads to connect an integrated circuit (IC) to a copper lead frame.
U.S. Pat. No. 6,550,666 B2 to Chew et al. discloses a method for forming a flip chip on leadframe semiconductor package.
U.S. Pat. No. 5,448,114 to Kondoh et al. discloses a semiconductor flip chip packaging having a perimeter wall.
U.S. Pat. No. 6,297,551 B1 discloses integrated circuit packages with improved EMI characteristics.
U.S. Pat. No. 4,430,690 to Chance et al. discloses a low inductance capacitor with metal impregnation and solder bar contact.
Accordingly, it is an object of the present invention to provide a improved bump design.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a die comprises a substrate and one or more pillar structures formed over the substrate in a pattern. The invention also includes the formation of a die by providing a substrate and forming one or more pillar structures over the substrate in a pattern.
The features and advantages of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
Initial Structure
As shown in
Structure 10 is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.
Embedded metal structure 12 may be electrically connected to one or more semiconductor devices formed within structure 10 and is preferably comprised of aluminum (Al), copper (Cu) or gold (Au) and is more preferably aluminum (Al) as will be used for illustrative purposes hereafter.
Overlying dielectric layer 14 is preferably comprised of nitride, silicon nitride (Si3N4), silicon oxide (SiO2) or polyimide and is more preferably silicon nitride as will be used for illustrative purposes hereafter.
The structure of
Formation of Metal Layer 15—
As shown in
Metal layer 15 is formed/spread over the whole of the wafer surface. Metal layer 15 preferably comprises a lower metal layer 16 and an upper metal layer 18. Lower metal layer 16 may be a metal barrier layer and is preferably titanium (Ti) or TiW and is more preferably Ti. Upper metal layer 18 is preferably copper (Cu).
Formation of Masking Layer 20—
As shown in
Masking layer 20 is preferably comprised of photoresist.
Patterning of Photoresist Layer 20—
As shown in
Plating of Metal Layer 26 Within Opening 22—
As shown in
Pillar metal layer 26 is lead-free and is preferably comprised of copper (Cu).
The pillar metal layer 26 may be coated with, for example, oxide or another material such as chromium, nickel, etc.
An optional layer of solder 28 is formed/plated over Cu pillar layer 26. Optional solder layer 28 may be roughly flush with the top surface of the patterned photoresist layer 20′ and may be overplated to preferably up to about 5 μm. Solder layer 28 is preferably comprised of: (1) from about 60 to 70% tin and from about 30 to 40% lead (Pb) for eutectic; (2) about 63% tin and 37% lead (Pb) for eutectic; (3) from about 99 to 100% tin and Sn3.5Ag for lead-free; or (4) 100% tin for lead-free and more preferably (2) about 63% tin and 37% lead (Pb) for eutectic or (4) 100% tin for lead-free.
Removal of Patterned Mask Layer 20′—
As shown in
Etching of Exposed Portions 30 of Cu Layer 15—
As shown in
Reflow of Copper Pillar Layer/Solder Layer 26/28—
Also as shown in
The total height of the pillar structure 34 after reflow is preferably from about 60 to 150 μm and more preferably about 100 μm.
Solder 28′ of pillar structure 34 provides a seal over the top of the Cu pillar layer 26 while it's sides are exposed.
It is noted that the bump can be at variable heights within the die.
The pillar structures 34 are used to connect die to die, die to leadframe and/or die to substrate.
Example Die Design 100—
The die perimeter may be used, and provides RF shielding, in Surface Acoustic Wave (SAW) devices, noise reduction, power current capacity, hermetic shield and may be used in RF devices, power devices and MEMs for noise isolation and current capacity.
The pillar structures of the present invention may be used in Surface Acoustic Wave (SAW) devices and power switches, for example, as well as MEMs.
Advantages of the Invention
The advantages of one or more embodiments of the present invention include:
1) the pillar structures of the present invention can conduct a higher flow of current;
2) better board level reliability performance with the use of the pillar structures of the present invention;
3) C4 (control collapse chip connect) feature of the pillar structures maintain required stand-off between the die and the package;
4) the pillar structures of the present invention provide improved heat dissipation; and
5) bigger area of metal/copper in a given pad opening provides better reliability.
While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.
Number | Name | Date | Kind |
---|---|---|---|
4430690 | Chance et al. | Feb 1984 | A |
5251806 | Agarwala et al. | Oct 1993 | A |
5448114 | Kondoh et al. | Sep 1995 | A |
6297581 | Dudderar et al. | Oct 2001 | B1 |
6550666 | Chew et al. | Apr 2003 | B2 |
6642136 | Lee et al. | Nov 2003 | B1 |
6847066 | Tahara et al. | Jan 2005 | B2 |
Number | Date | Country |
---|---|---|
2000243765 | Sep 2000 | JP |
2000243783 | Sep 2000 | JP |
Number | Date | Country | |
---|---|---|---|
20050077624 A1 | Apr 2005 | US |