Patent Application
20240071990
The present disclosure generally relates to semiconductor devices, and more particularly relates to extended bond pad for semiconductor device assemblies.
Microelectronic devices generally have a die (i.e., a chip) that includes integrated circuitry with a high density of very small components. Typically, dice include an array of very small bond pads electrically coupled to the integrated circuitry. The bond pads are external electrical contacts through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry. After dice are formed, they are “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines. Conventional processes for packaging dice include electrically coupling the bond pads on the dice to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the dice to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact).
The drawings illustrate only example embodiments and are therefore not to be considered limiting in scope. The elements and features shown in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the example embodiments. Additionally, certain dimensions or placements may be exaggerated to help visually convey such principles. In the drawings, the same reference numerals used in different embodiments designate like or corresponding, but not necessarily identical, elements.
Chip-on-Board (COB), which is also described as direct chip attachment (DCA), refers semiconductor device assembly technology wherein a semiconductor chip or die is directly mounted or attached on a circuit board or a substrate. Instead of complex packaging procedures involved in traditional assembly technologies, the DCA process mainly includes a semiconductor chip mounting step, e.g., attaching flipped semiconductor chip on the substrate. This DCA assembly may not require additional wire bonding since it employs a flipped chip facing downward on the substrate and having bumped bond pads, e.g., copper pillar bumps, that connect directly to designated bond pads on the substrate. The DCA process may also include applying a die attach adhesive material such as solder paste to the flipped chip or substrate and mounting the chip on the substrate over the die attach adhesive material. Aside from the chip attachment, it is also necessary to underfill the bond-line-thickness (BLT) region between the semiconductor chip and the substrate to protect the active surface and pillar bumps of the semiconductor chip from potential thermo-mechanical and chemical damages during the semiconductor device assembly. The DCA technology simplifies the overall process of manufacturing the semiconductor device and improves its performance by shortening the interconnection paths therein.
Of many issues observed in the DCA semiconductor device assembly during the continued scaling of semiconductor packages, solder bridging defect takes the top of the list. A solder bridging defect is formed when two adjacent solder balls between the flipped chip and substrate board that should not be electrically connected are inadvertently connected, e.g., during the DCA process. Specifically, the solder bridging defect may exist at the BLT region of flipped chip and the substrate, and between adjacent copper pillar bumps. This solder bridging defect will form an electrically short semiconductor device assembly and may cause various damages on the semiconductor device. An incomplete underfill material flow in the BLT region or an excessive solder volume between the pillar bumps of the flipped chip and bond pads of the substrate board likely can cause the solder bridging defect in the DCA process for semiconductor device assembly.
To address these challenges and others, the present technology applies extended bond pads in the semiconductor device assembly. In particular, the extended bond pads are fabricated on a frontside surface of a substrate or a bottom semiconductor wafer. The DCA process is used to bond pillar bumps of a top semiconductor device to corresponding extended bond pads of a bottom substrate for the semiconductor device assembly. The extended bond pads can be surrounded or are formed in a patterned solder mask layer disposed on the frontside surface of the bottom substrate. Specifically, the extended bond pads include an upper portion that protrudes from the top surface of the solder mask layer. In the present technology, the extended bond pads of the bottom substrate may have various cross-sectional profiles. For example, the extended bond pads may have a top flat surface smaller than its bottom surface. In another example, the top surface of the extended bond pads may have a concave profile facing towards the pillar bumps of the semiconductor device in the semiconductor device assembly.
The extended bond pads of the bottom substrate provide additional height for the BLT between the top semiconductor device and the bottom substrate, which eases the non-conductive under fill material flowing in the BLT region and reduces the risk of voids. In addition, the additional height of the extended bond pads reduces the volume of solder paste needed in the DCA process, helping eliminate the risk of solder bridging defects between adjacent bond pads in the semiconductor device assembly. Moreover, for extended bond pads having the concave profile on their top surface, the solder material is contained or self-aligned above the concave profile, further reducing the risk of solder ball squeezing out and bridging with adjacent bonding structures.
In addition, the substrate 120 includes a solder mask layer 122, a plurality of bond pads 124, a plurality of vias 128, and solder bumps 126 that disposed above each of the plurality of bond pads 124. The substrate 120 also includes a plurality of redistribution layers 127 that are interconnected by the plurality of vias 128 and that provide electrical connection paths between the bond pads 124 on the frontside surface of the substrate 120 and the solder bumps 129 on the backside surface of the substrate 120. In this example, the plurality of bond pads 124 are surrounded by the solder mask layer 122, e.g., having the solder mask layer 122 disposed between adjacent bond pads 124. Specifically, the solder mask layer 122 has a top surface higher than that of the plurality of bond pads 124. As shown in
As shown in
As the semiconductor devices scales, the pitch distance of the bond pads and the pillar bumps may reduce accordingly, causing a reduced spacing between the adjacent solder 132 after the DCA process. The solder bridging defect 134 is likely to form due to the reduced pitch distance of the bond pads 122 and excessive volume of the solder material applied on the pillar bumps 114 and on the bond pads 122, in the DCA process. In addition, the BLT region between the frontside surface of the semiconductor device 110 and the frontside surface of the substrate 120 is likely to scale down in order to increase the semiconductor device packaging density, which causes more challenges in flowing non-conductive underfill materials in the BLT region.
In some embodiments, the pillar bumps 214 including the cap solder 216 are used to make electrical interconnects between the semiconductor die 210 and the substrate 220. For example, the cap solders 216 may be compressed and heated to bond on the plurality of extended bond pads 226 on the top surface of the substrate 220. The plurality of extended bond pads 226 may be connected to electrical traces 228 through corresponding vias 224. The electrical traces 228 under the solder mask layer 222 may be electrically isolated and configured to provide electrical paths to the plurality of bond pads 226 through corresponding vias 224. Additionally, the top surface of the substrate 220 may be covered by the solder mask layer 222 which surrounds the plurality of extended bond pads 226. In this example, the semiconductor device 210 is flipped and positioned adjacent to the substrate 210 prior to the bonding by the DCA process. Here, the plurality of pillar bumps 214 may be made of materials including copper, tungsten, molybdenum, nickel, titanium, tantalum, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, or combinations thereof. The cap solder 216 may be made of solder paste materials. Further, the solder mask layer 222 may be made of polymer materials. In this example, the substrate 220 can be a printed circuit board (PCB).
In some embodiments, the plurality of extended bond pads 226 may have a bottom surface substantially planar (e.g., within 1° of parallel, within 3° of parallel, within 5° of parallel, or within 10° of parallel) to a bottom surface of the solder mask layer 222. Specifically, the solder mask layer 222 which may have a height close to 20 μm and the plurality of extended bond pads 226 may have a thickness in vertical axis ranging from 25 μm to 30 μm. As shown, each of the plurality of extended bond pads 226 is at least partially extending above the top surface of the solder mask layer 222. The top surface of each of the plurality of extended bond pads 226 can be higher than that of the solder mask layer by 5 μm to 10 μm. In addition, the pillar bumps 214 of the semiconductor device 210 may have a diameter close to 80 μm. Here, the plurality of extended bond pads 226 may be made of materials including copper, tungsten, molybdenum, nickel, titanium, tantalum, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, or combinations thereof.
In some embodiments, each of the plurality of extended bond pads 226 may include an upper portion higher than the top surface of the solder mask layer 222 and a lower portion in parallel to the solder mask layer 222. As described, the upper portion of the bond pads 226 may have a height ranging from 5 μm to 10 μm and comprises various cross-sectional shapes. For example, the upper portion of each of the plurality of extended bond pads 226 may be in a trapezoid shape and the lower portion of each of the plurality of extended bond pads 226 may be in a rectangular shape. In this example, the plurality of extended bond pads 226 may have a smaller top surface than the opening of the solder mask layer 222, e.g., having a diameter for its top surface close to 80 μm or less and a diameter for its bottom surface close to 120 μm or less.
In some embodiments, the plurality of extended bond pads 226 may be processed by a selected area plating process. For example, a first bond pad layer may be deposited in the patterned solder mask layer 222 by a plating process so as to form the lower portion of the plurality of extended bond pads 222. The first bond pad layer may be continuous between adjacent bond pads 226. The portion of the first bond pad layer between adjacent bond pads can be patterned and filled by a dry resist material therein. A dry resist film can be then patterned above the first bond pad layer to expose regions above the first bond pad layer for processing the upper portion of the bond pads 226. A second bond pad layer can then be deposited by the plating process in the exposed region of the dry resist film to form the upper portion of the plurality of extended bond pad 226. After stripping off the dry resist material and the dry resist film, an etching process, e.g., a flash etching process, may be applied on the first and second bond pad layers to complete the plurality of extended bond pad 226 as shown in
As shown in
Now turning to
As shown in
In some embodiments, the plurality of extended bond pads 326 may extend out of the solder mask layer 322, e.g., by 5 μm to 10 μm. Specifically, each of the plurality of extended bond pads 326 may have a concave profile on its top surface. For example and as shown in
The plurality of extended bond pads 326 with the concave profile on its frontside surface can be processed by the selected area plating process following by a laser etching process. For example, extended bond pads similar to bond pads 226 described in
Alternatively, the plurality of extended bond pads 326 with the concave profile may be processed by a half etch process. For example, a thick bond pad layer may be deposited in openings of patterned solder mask layer 322. The thick bond pad layer may have a thickness corresponding to or slightly higher than target extended bond pads 326. A dry resist film can be patterned above the thick bond pad layer to expose openings having a width close to the chord length of the target concave profile. Then a flash etching process can be applied on the patterned dry resist layer to remove the bond pad material form the top surface of the thick bond pad layer. The concave profile can be formed on the etched bond pad layers due to a loading effect of the flash etching process. Here after, the etched bond pad layer can be further processed in a second flash etching process to form the plurality of extended bond pads 326 as shown in
As shown in
The method 400 also includes patterning the first bond pad layer to form isolations between adjacent bond pads and filling the patterned bond pad layer with a dry resist material, at 404. For example, the first bond layer can be patterned to remove bond pad material between adjacent bond pads 226 as shown in
In addition, the method 400 includes depositing a dry resist film above the first bond pad layer and patterning the dry resist film, at 406. For example, the second dry resist film can be deposited above the first bond pad layer and patterned to expose a top surface region of each of the plurality of bond pads 226.
The method 400 can also include depositing bond pad material in the patterned dry resist film and above the first bond pad layer, at 408. For example, a second bond pad layer, e.g., a copper layer, can be deposited in the patterned second dry resist film above the solder mask layer 222 in a plating process. Specifically, the second bond pad layer forms the upper portion of the plurality of bond pads 226.
Further, the method 400 includes stripping off the dry resist material and the patterned dry resist film, at 410. For example, the dry resist material disposed between adjacent bond pads 226 and above the first bond pad layer can be stripped off from the substrate 220.
Lastly, the method 400 includes flash etching the deposited bond pad material and the patterned first bond pad layer to form a plurality of extended bond pads, at 412. For example, the flashing etching process can form the plurality of bond pads 226 having a top surface smaller than the opening of the surrounding solder mask layer 222 due to the loading effect of the flashing etching process. As shown in
Turning to
The method 500 also includes patterning the bond pad layer to form isolation between adjacent bond pads and filling the patterned bond pad layer with a dry resist material, at 504. For example, the thick bond pad layer can be patterned, and bond pad material disposed between adjacent bond pads 326 can be etched out to form isolation therebetween. Further, a dry resist material can be deposited in the patterned thick bond pad layer and followed by a surface planarization process.
In addition, the method 500 includes depositing a dry resist film above the bond pad layer and patterning the dry resist film, at 506. For example, a dry resist film can be deposited above the thick bond pad layer and the solder mask layer 322. Specifically, the dry resist film can be patterned to expose a top surface of each of the plurality of bond pads 326 corresponding to the concave profiles shown in
The method 500 also includes etching the bond pad layer through the patterned dry resist film by a first flash etching process, at 508. For example, a first flash etching can be conducted on the patterned dry resist film and exposed top surface of the plurality of bond pads 326. The flash etching process may have a loading effect, e.g., etching the center of the patterned trench faster than the edge of the patterned trench, therefore forming the concave profile on the top surface of the plurality of bond pads 326. Specifically, the first flash etching process can be configured to control the height of a lower rim/center of the concave profile close to or higher than the top surface of the solder mask layer 326.
Moreover, the method 500 includes stripping off the dry resist material and the dry resist film, at 510. For example, the dry resist material isolates adjacent bond pads 326 and dry resist layer above the thick bond pad layer can be stripped off from the substrate 320.
Lastly, the method 500 includes etching the bond pad layer by a second flash etching process to form a plurality of extended bond pads on the frontside surface of the substrate, at 512. For example, a second flash etching process can be conducted on the bond pad layer to remove residual bond pad material disposed between adjacent bond pads 326 and the top portion of the thick bond pad layer. The second flash etching process may also additionally polish the concave profile on the top surface of the plurality of bond pads 326.
Any one of the semiconductor structures described above with reference to
Specific details of several embodiments of semiconductor devices, and associated systems and methods, are described below. A person skilled in the relevant art will recognize that suitable stages of the methods described herein can be performed at the wafer level or at the die level. Therefore, depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated, die-level substrate. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.
In accordance with one aspect of the present disclosure, the semiconductor devices illustrated above could be memory dice, such as dynamic random access memory (DRAM) dice, NOT-AND (NAND) memory dice, NOT-OR (NOR) memory dice, magnetic random access memory (MRAM) dice, phase change memory (PCM) dice, ferroelectric random access memory (Fe RAM) dice, static random access memory (SRAM) dice, or the like. In an embodiment in which multiple dice are provided in a single assembly, the semiconductor devices could be memory dice of a same kind (e.g., both NAND, both DRAM, etc.) or memory dice of different kinds (e.g., one DRAM and one NAND, etc.). In accordance with another aspect of the present disclosure, the semiconductor dice of the assemblies illustrated and described above could be logic dice (e.g., controller dice, processor dice, etc.), or a mix of logic and memory dice (e.g., a memory controller die and a memory die controlled thereby).
The devices discussed herein, including a memory device, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.
The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and appended claims. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.
As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”
As used herein, the terms “top,” “bottom,” “over,” “under,” “above,” and “below” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation.
It should be noted that the methods described above describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined.
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Rather, in the foregoing description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.
