Patent Application
20190304917
The present disclosure generally relates to semiconductor devices. In particular, the present disclosure relates to wafer level packaging.
Fan-out wafer level packaging (FOWLP) is produced by the formation of a redistribution layer (RDL) with under bump metallization (UBM) on a support carrier including silicon or glass and a temporary sacrificial layer. Die-to-wafer bonding is performed followed by wafer molding. The process to produce the FOWLP further requires specialized debonding equipment and an extra debonding process. In particular, the debonding step is required at the interface between the support carrier and RDL prior to wafer bumping. This leads to higher costs and yield loss. Moreover, FOWLP for radio frequency (RF) applications requires additional space for an inductor or antenna which leads to higher costs due to a larger package size.
A need therefore exists for efficient methodology enabling formation of a high density FOWLP with reduced size and the resulting device.
An aspect of the present disclosure is using a carrier wafer during formation of a high density FOWLP. The carrier wafer remains in the final package structure and the RDL is formed on the carrier wafer. Another aspect of the present disclosure is including an antenna or inductor formed on the carrier wafer.
Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
According to the present disclosure, some technical effects may be achieved in part by a method including: forming vias in a first surface of a carrier wafer; filling the vias with a metal; forming a RDL over the carrier wafer, the RDL being in contact with the metal filled vias; attaching a semiconductor die to the RDL; forming a wafer mold over the semiconductor die; and removing a portion of the carrier wafer to expose the metal filled vias on a second surface of the carrier wafer.
Aspects of the present disclosure include filling the vias with contacts on the first surface of the carrier wafer. Other aspects include forming the vias in the carrier wafer with laser ablation. Another aspect includes removing the portion of the carrier wafer by way of grind. Further aspects include forming solder bumps or balls over the exposed metal filled vias on the second surface of the carrier wafer. Another aspect includes forming a plurality of RDLs over the carrier wafer.
Another aspect of the present disclosure is a method including: forming vias in a first surface of a carrier wafer; filling the vias with a metal; forming a first RDL over the carrier wafer, the first RDL being in contact with the metal filled vias; attaching a semiconductor die to the first RDL; forming a wafer mold over the semiconductor die; removing a portion of the carrier wafer to expose the metal filled vias on a second surface of the carrier wafer; and forming a dielectric passivation layer on second surface of the carrier wafer, the dielectric passivation layer including an antenna or inductor.
Aspects of the present disclosure include filling the vias with contacts on the first surface of the carrier wafer. Aspects of the present disclosure also include forming the vias in the carrier wafer with laser ablation. Other aspects include removing the portion of the carrier wafer by way of grinding. Another aspect includes forming solder bumps or balls over the dielectric passivation layer in contact with the metal filled vias on the second surface of the carrier wafer. Further aspects include the first RDL having a plurality of layers over the carrier wafer.
A further aspect of the present disclosure is a device including: metal vias formed in a carrier wafer extending from a first surface of the carrier wafer to a second surface of the carrier wafer; a RDL formed over the carrier wafer, the RDL being in contact with the metal filled vias; a semiconductor die formed over the RDL; a wafer mold formed over the semiconductor die; and solder bumps or balls formed on the second surface of the carrier wafer and in contact with the metal filled vias.
Aspects of the present disclosure include the metal filled vias being copper and including copper contacts formed on the first surface of the carrier wafer in contact with metal wiring of the RDL. Aspects of the present disclosure also include the RDL having a plurality of layers. Other aspects include the carrier wafer being a resin or polymer, and the wafer mold being an organic resin of fused silica. Another aspect includes the device being a fan-out wafer level package. Further aspects include a dielectric passivation layer formed between the solder bumps or balls and the carrier wafer. Another aspect includes the dielectric passivation layer having an antenna. Yet another aspect includes the dielectric passivation layer having an inductor.
Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
The present disclosure addresses and solves the current problem of needing specialized debonding equipment and extra processing steps to remove a support carrier and sacrificial layer during FOWLP production. The problem is solved, inter alia, by using a carrier wafer as the support carrier which remains in the final FOWLP, thereby eliminating the need for an extra and costly debonding step.
Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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The embodiments of the present disclosure can achieve several technical effects including reducing the size and cost during high density FOWLP. Embodiments of the present disclosure can also enjoy utility in various industrial applications as, for example, semiconductor fabrication plants that produce components used in microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure enjoys industrial applicability in any of various types.
In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure can use various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
