Claims
- 1. A method of joining a chip to a substrate, comprising:
- providing a substantially planar structure between a chip and a substrate;
- providing the planar structure with through holes;
- providing a flowable conductive material; and
- causing the flowable conductive material to flow into the through holes and make an electrical connection between the chip and the substrate.
- 2. A method of joining a chip to a substrate, comprising:
- bringing a chip having first solder balls on a face thereof into face-to-face relationship with a substrate having corresponding second solder balls on a face thereof;
- providing a separate and distinct preformed planar structure having two faces, and through holes extending from one face of the preformed planar structure to the other face of the preformed planar structure;
- interposing the preformed planar structure between the faces of the chip and the substrate, one face of the preformed planar structure in contact with the face of the chip and the other face of the preformed planar structure in contact with the face of the substrate; and
- elevating the temperature of the chip and the substrate sufficiently to cause the first solder balls to fuse directly to the second solder balls, thereby forming solder joints within the through holes.
- 3. A method, according to claim 2, wherein:
- the solder balls on the chip are solderable metallized surfaces.
- 4. A method, according to claim 2, wherein:
- the solder balls on the substrate are solderable metallized surfaces.
- 5. A method, according to claim 2, wherein:
- the solder balls on the chip are pads.
- 6. A method, according to claim 2, wherein:
- the solder balls on the substrate are pads.
- 7. A method, according to claim 2, further comprising:
- providing at least one face of the preformed planar structure with a skin which will soften and shrink when subjected to elevated temperatures, thereby drawing the chip closer to the substrate.
- 8. A method, according to claim 7, wherein:
- both faces of the preformed planar structure are provided with a skin which will soften and shrink when subjected to elevated temperatures, thereby drawing the chip closer to the substrate.
- 9. A method, according to claim 7, wherein:
- the skin provides a cushion for the faces of the chip and the substrate.
- 10. A method according to claim 2, wherein:
- the preformed planar substrate is applied to the chip; and
- the chip is subsequently brought into face-to-face relationship with the substrate.
- 11. A method according to claim 2, wherein:
- the preformed planar substrate is applied to the substrate; and
- the chip is subsequently brought into face-to-face relationship with the substrate.
- 12. A method, according to claim 2, wherein:
- the preformed planar structure provides a controlled spacing between the chip and the substrate.
- 13. A method, according to claim 2, wherein:
- the preformed planar structure establishes a minimum gap between the chip and the substrate.
- 14. A method according to claim 2, wherein:
- the preformed planar structure is provided with through holes in registration with the solder balls and corresponding solder balls.
- 15. A method according to claim 14, wherein:
- the through holes are sized to establish a predetermined mechanical structure of solder joints formed by the solder balls and corresponding solder balls when fused together.
- 16. A method according to claim 2, wherein:
- the preformed planar structure has a planar core and two opposing faces.
- 17. A method according to claim 16, wherein:
- the faces are provided with a skin; and
- further comprising:
- elevating the temperature of the preformed planar structure sufficiently to cause the skin to soften and draw the chip together.
CROSS REFERENCE TO RELATED APPLICATIONS
This is a division of copending, commonly-owned U.S. patent application Ser. No. 07/775,009, filed Oct. 11, 1991, now U.S. Pat. No. 5,168,346, which is a division of U.S. patent application Ser. No. 07/576,182 filed Aug. 30, 1990, now U.S. Pat. No. 5,111,279, which is a continuation of U.S. patent application Ser. No. 07/400,572 filed Aug. 28, 1989, now abandoned.
US Referenced Citations (62)
Foreign Referenced Citations (1)
Number |
Date |
Country |
57-210638(A) |
Dec 1982 |
JPX |
Divisions (2)
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Number |
Date |
Country |
Parent |
775009 |
Oct 1991 |
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Parent |
576182 |
Aug 1990 |
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Continuations (1)
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Number |
Date |
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Parent |
400572 |
Aug 1989 |
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