Patent Application
20240404898
Semiconductor devices and integrated circuits used in a variety of electronic applications, such as cell phones and other mobile electronic equipment, are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies have been developed for the wafer level packaging.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “over”, “overlying”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
In some embodiments, the buffer layer includes a de-bonding layer 104A and a dielectric layer 104B, wherein the de-bonding layer 104A is located in between the carrier 102 and the dielectric layer 104B. In certain embodiments, the de-bonding layer 104A is disposed on the carrier 102, and the material of the de-bonding layer 104A may be any material suitable for bonding and de-bonding the carrier 102 from the above layer(s) (e.g., the dielectric layer 104B) or any wafer(s) disposed thereon. In some embodiments, the de-bonding layer 104A may include a release layer (such as a light-to-heat conversion (“LTHC”) layer) or an adhesive layer (such as an ultra-violet curable adhesive or a heat curable adhesive layer). In some embodiments, the dielectric layer 104B may be formed above the de-bonding layer 104A. The dielectric layer 104B may be made of dielectric materials such as benzocyclobutene (“BCB”), polybenzoxazole (“PBO”), or any other suitable polymer-based dielectric material. Furthermore, the top surface of the dielectric layer 104B may have a high degree of coplanarity.
It is noted that the materials of the carrier 102, the de-bonding layer 104A and the dielectric layer 104B are not limited to the descriptions of the embodiments. In some alternative embodiments, the dielectric layer 104B may be optionally omitted; in other words, merely the de-bonding layer 104A is formed over the carrier 102. In certain embodiments, a die-attach film may be directly formed on the de-bonding layer 104A for the attachment to above components.
Referring to
In an alternative embodiment, the through insulator vias 108 may be formed by forming a seed layer (not shown) on the dielectric layer 104B; forming the mask pattern with openings exposing portions of the seed layer; forming the metallic material on the exposed portions of the seed layer to form the through insulator vias 108 by plating; removing the mask pattern; and then removing portions of the seed layer exposed by the through insulator vias 108. For example, the seed layer may be a titanium/copper composited layer. For simplification, only four through insulator vias 108 are illustrated in
In some embodiments, one or more semiconductor dies 106 may be picked and placed on the dielectric layer 104B. For example, each of the semiconductor dies 106 have an active surface AS, and a backside surface BS opposite to the active surface AS. In some embodiments, a die attach film 105 is attached on the backside surface BS of the semiconductor dies 106 for bonding the semiconductor dies 106 to a top surface of the dielectric layer 104B. By using the die attach film 105, a better adhesion between the semiconductor dies 106 and the dielectric layer 104B is ensured. In the exemplary embodiment, two semiconductor dies 106 are illustrated on the buffer layer (including 104A, 104B). However, the disclosure is not limited thereto. In other embodiments, the number of semiconductor dies 106 disposed on the carrier 102 may be adjusted based on product requirement.
In the exemplary embodiment, the semiconductor dies 106 include a semiconductor substrate 106A, a plurality of conductive pads 106B, a passivation layer 106C, a post passivation layer 106D, a plurality of conductive posts or conductive vias 106E, and a protection layer 106F. As illustrated in
In some embodiments, the semiconductor substrate 106A is a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and further includes several microelectronic layers formed therein. For example, these layers may include conductor layers, semiconductor layers, dielectric layers, active devices (e.g., transistors or the like) and passive devices (e.g., resistors, capacitors, inductors or the like), or the like (all not shown). The dielectric layer may be silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, high-k dielectric materials, or combinations thereof. In one embodiment, the dielectric layers include extreme low dielectric constant (ELK) films. As used herein, low dielectric constant materials are those films having a dielectric constant between 3.0 to 2.5 and extreme low dielectric constant films are those films having a dielectric constant below 2.5 extending to dielectric constants below 2.0. The ELK films may include any ELK films including but not limited to inorganic, organic, and hybrid dielectric materials.
In some embodiments, the conductive pads 106B may be aluminum pads, copper pads or other suitable metal pads. The passivation layer 106C may be a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer or a dielectric layer formed of any suitable dielectric materials. Furthermore, in some embodiments, the post-passivation layer 106D is optionally formed over the passivation layer 106C. The post-passivation layer 106D covers the passivation layer 106C and has a plurality of contact openings. The conductive pads 106B are partially exposed by the contact openings of the post passivation layer 106D. The post-passivation layer 106D may be a benzocyclobutene (BCB) layer, a polyimide layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed by other suitable polymers. In some embodiments, the conductive posts or conductive vias 106E are formed on the conductive pads 106B by plating. In some embodiments, the protection layer 106F is formed on the post passivation layer 106F covering the conductive posts or conductive vias 106E so as to protect the conductive posts or conductive vias 106E.
In some embodiments, when more than one semiconductor dies 106 are placed on the dielectric layer 104B, the semiconductor dies 106 may be arranged in an array, and when the semiconductor dies 106 are arranged in an array, the through insulator vias 108 may be classified into groups. The number of the semiconductor dies 106 may correspond to the number of the groups of the through insulator vias 108. In the illustrated embodiment, the semiconductor dies 106 may be picked and placed on the dielectric layer 104B after the formation of the through insulator vias 108. However, the disclosure is not limited thereto. In some alternative embodiments, the semiconductor dies 106 may be picked and placed on the dielectric layer 104B before the formation of the through insulator vias 108.
In some embodiments, the semiconductor dies 106 may be selected from application-specific integrated circuit (ASIC) chips, analog chips (for example, wireless and radio frequency chips), digital chips (for example, a baseband chip), integrated passive devices (IPDs), voltage regulator chips, sensor chips, memory chips, or the like. The disclosure is not limited thereto.
Referring to
In some embodiments, the insulating material 110 is made by a molding composition that comprises (a) fillers, (b) resin, (c) hardener and (d) stress relation agents. In some embodiments, the fillers include inorganic fillers such as silicon oxide (SiO2), or the like, that are added into the molding composition to optimize coefficient of thermal expansion (CTE) of the insulating material 110. In some embodiments, the resin includes resins such as epoxy resins, phenolic resins, silicon-containing resins, or other suitable resins. In certain embodiments, the epoxy resins include diepoxy resin or multifunctional epoxy resin. In some embodiments, the diepoxy resin includes but are not limited to: (i) 1,6-bis(2,3-epoxypropoxy)naphthalene, (ii) 2,6-bis(2,3-epoxypropoxy)acetophenone, (iii) 2,2-Bis(4-glycidyloxyphenyl)propane, (iv) 3.4-Epoxycyclohexylmethyl3,4-epoxycyclohexanecarboxylate. In some embodiments, the multifunctional epoxy resin includes but are not limited to: (i) 1-(2,3-epoxypropoxy)-2,2-bis[(2,3-epoxypropoxy)methyl]butane, (ii) triphenylolmethane triglycidyl ether, (iii) 1,1,1-tris(4-hydroxyphenyl)ethane triglycidyl ether, (iv) tris(oxiranylmethyl) benzene-1,3,5-tricarboxylate. In some embodiments, the hardener may be an anhydride-based hardener or an amine-based hardener. In some embodiments, the anhydride-based hardener includes but are not limited to: (i) methylhexahydrophthalic anhydride, (ii) 3-methylhexahydrophthalic anhydride, (iii) 5-methylhexahydrophthalic anhydride, (iv) phenylmaleic anhydride. In certain embodiments, the amine-based hardener includes but are not limited to: (i) 1,2-diaminocyclohexane, (ii) 4,4′-diaminodiphenylsulfone, (iii) 2,2′-oxybis(methylene)dianiline, (iv) diethylenetriamine.
Furthermore, in some embodiments the stress relaxation agent is composed of silicone oil, and include at least one compound selected from the group of compounds represented by formula (1):
wherein, in formula (1), X is independently CH3, C2H5, C3H7, C6H5, C10H7, C12H9, Y is independently CH3, C2H5, C3H7, C6H5, C10H7, C12H9, R is independently CH2, C2H4, C3H6, OCH2, OC2H4, OC3H6, OC2H2, C2H2O, C3H4O, C4H6O, and n is 1-100.
In some embodiments, the stress relaxation agent includes a compound represent by formula (1-A):
For example, in one embodiment, the molding composition includes the compound represent by formula (1-A) as the main component, while other compounds selected from the group of compounds represented by formula (1) may be optionally contained. In certain embodiments, compounds that cannot read into formula (1) are excluded as the stress relaxation agent.
In the exemplary embodiment, based on a total weight of the molding composition. the fillers are contained in an amount of 80% by weight to 90% by weight, the resin is contained in an amount of 1% by weight to 15% by weight, the hardener is contained in an amount of 1% by weight to 15% by weight, and the stress relaxation agent composed of silicone oil is contained in an amount of 0.5% by weight to 5% by weight. In some embodiments, if an amount of the stress relaxation agent in the molding composition is less than 0.5%, then a swelling value of the molding composition (or the formed insulating material 110) will be too high. In certain embodiments, if an amount of the stress relaxation agent in the molding composition is more than 5%, then the physical properties of the insulating material 110 such as the coefficient of thermal expansion, young's modulus, glass transition temperature, and warpage may be affected. In some embodiments, the swelling value of the molding composition is controlled in a range of 0.1% to 0.4%. In certain embodiments, the swelling value of the molding composition is controlled in a range of 0.17% to 0.35%. A thermal mechanical analyzer (TMA) may be used for measuring and calculating the swelling value, whereby the measured sample was ramped to 130° C. (10° C./minute) and held isothermal for 5 minutes at 130° C. during measurement.
In the exemplary embodiment, when the type of stress relaxation agent and the amount of stress relaxation agent used in the molding composition are as designated above, then a swelling strain of the formed insulating material 110 may be reduced. As such, even under high thermal and humidity conditions, the molding composition may reduce hydrogen bonding formation and block water cluster, and the insulating material 110 (or mold) having low swelling can be achieved. Therefore, the prevention of water/moisture absorption to the ELK films in the semiconductor die 106 may be achieved, and an ELK film delamination issue commonly observed in integrated fan-out packages may be resolved. On the other hand, if the stress relaxation agent is not used in the molding composition, an ELK film delamination issue may occur, which may further induce DRAM (dynamic random-access memory) retention failure.
Referring to
In the illustrated embodiment, the insulating material 110 is polished to form an insulating encapsulant 110′. In some embodiments, the top surface 110-TS of the insulating encapsulant 110′, the top surface 108-TS of the through insulator vias 108, the top surface 106-TS of the conductive posts 106E, and the top surface of the polished protection layer 106F are coplanar and levelled with one another. In some embodiments, after the mechanical grinding or chemical mechanical polishing (CMP) steps, a cleaning step may be optionally performed. For example, the cleaning step is preformed to clean and remove the residue generated from the planarization step. However, the disclosure is not limited thereto, and the planarization step may be performed through any other suitable methods.
Referring to
In some embodiments, the formation of the redistribution layer 112 includes sequentially forming one or more dielectric layers 112A, and one or more metallization layers 112B in alternation. In certain embodiments, the metallization layers 112B are sandwiched between the dielectric layers 112A. Although only two layers of the metallization layers 112B and three layers of dielectric layers 112A are illustrated herein, however, the scope of the disclose is not limited by the embodiments of the disclosure. In other embodiments, the number of metallization layers 112B and the dielectric layers 112A may be adjusted based on product requirement. In some embodiments, the metallization layers 112B are electrically connected to the conductive posts 106E of the semiconductor dies 106. Furthermore, the metallization layers 112B are electrically connected to the through insulator vias 108.
In some embodiments, the material of the dielectric layers 112A may be polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof or the like, which may be patterned using a photolithography and/or etching process. In some embodiments, the dielectric layers 112A are formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like. The disclosure is not limited thereto.
In some embodiments, the material of the metallization layer 112B may be made of conductive materials formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, which may be patterned using a photolithography and etching process. In some embodiments, the metallization layer 112B may be patterned copper layers or other suitable patterned metal layers. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of clements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc.
After forming the redistribution layer 112, a plurality of conductive pads 114 may be disposed on an exposed top surface of the topmost layer of the metallization layers 112B for electrically connecting with conductive balls. In certain embodiments, the conductive pads 114 are for example, under-ball metallurgy (UBM) patterns used for ball mount. As shown in
Referring still to
Referring to
After debonding the carrier 102, a dicing process is performed along the dicing lines DL to separate individual packages. For example, the dicing is performed to cut through the dielectric layer 104B, the insulating encapsulant 110′ and the redistribution layer 112 to form the separated package PK1 (first package) as shown in
After forming the backside redistribution layer 103 on the de-bonding layer 104A, the same steps illustrated in
Referring to
In some embodiments, bonding wires 330 are used to provide electrical connections between the semiconductor chips 320 and pads 340 (such as bonding pads). In some embodiments, an insulating encapsulant 360 is formed to encapsulate the semiconductor chips 320 and the bonding wires 330 to protect these components. In some embodiments, through insulator vias (not shown) may be used to provide electrical connection between the pads 340 and conductive pads 350 (such as bonding pads) that are located on another surface (e.g. bottom surface) of the substrate 310. In certain embodiments, the conductive pads 350 are electrically connected to the semiconductor chips 320 through these through insulator vias (not shown). In some embodiments, the conductive pads 350 of the second package PKX are electrically connected to the through insulator vias 108 of the first package PK1 through electrical connectors 202. In some embodiments, an underfill 370 is further provided to fill in the spaces between the electrical connectors 202 so as to protect the electrical connectors 202. After stacking the second package PKX on the first package PK1 and providing electrical connection therebetween, a package-on-package structure PoPl (or semiconductor package) according to some exemplary embodiments can be fabricated.
To prove that the molding composition of the embodiments can be used to lower the swelling strain, the swelling value of different molding compositions including and excluding the stress relaxation agents are compared, and the results are shown in Table 1.
Referring to Table 1, comparative compositions 1 and 2 are conventional compositions that exclude the use of stress relation agents, while example compositions 1 and 2 are molding compositions of the present disclosure whereby stress relaxation agents are added. As shown in comparative compositions 1 and 2 of Table 1, when stress relation agents are not added in the molding composition, the swelling value of the composition is in a range of 0.8% to 0.9%. In comparison, if 0.5˜5% by weight of stress relaxation agent is added into the composition, then as shown in example compositions 1 and 2, the swelling value may be significantly reduced to a range of 0.17% to 0.35%.
Furthermore, it is found that the mold formed by the example compositions 1 and 2 have physical properties (coefficient of thermal expansion, young's modulus, glass transition temperature, and warpage, etc.) that are comparable to the mold formed by comparative compositions 1 and 2. This indicates that the example compositions 1 and 2 can maintain the suitable physical properties of conventional mold, while further reducing the swelling value. An evaluation of the delamination length of the mold under high thermal and humidity conditions after 300 hours using the scanning electron microscope (SEM) also shows that the mold formed by example compositions 1 and 2 have 50% to 60% reduction in delamination length as compared to the mold formed by the comparative compositions 1 and 2. These experimental results prove that the molding compositions of the present disclosure will further reduce the swelling value, and improve ELK delamination resistance.
According to the above embodiments, the molding composition for a semiconductor package includes at least a stress relaxation agent composed of silicone oil, which is contained in an amount of 0.5% by weight to 5% by weight based on a total weight of the molding composition. As such, the molding composition may reduce hydrogen bonding formation and block water cluster, and the insulating encapsulant formed by the molding composition will have low swelling properties. Therefore, the prevention of water/moisture absorption to the ELK films in the semiconductor die may be achieved, and an ELK delamination issue commonly observed in integrated fan-out packages may be resolved.
In accordance with some embodiments of the present disclosure, a molding composition for a semiconductor package includes fillers, a resin, a hardener and a stress relaxation agent. The fillers are contained in an amount of 80% by weight to 90% by weight based on a total weight of the molding composition. The resin is contained in an amount of 1% by weight to 15% by weight based on a total weight of the molding composition. The hardener is contained in an amount of 1% by weight to 15% by weight based on a total weight of the molding composition. The stress relaxation agent is composed of silicone oil, and is contained in an amount of 0.5% by weight to 5% by weight based on a total weight of the molding composition.
In accordance with some other embodiments of the present disclosure, a semiconductor package includes a first package. The first package includes a semiconductor die, an insulating encapsulant, and a redistribution layer. The insulating encapsulant is surrounding the semiconductor die, wherein the insulating encapsulant is formed from a molding composition comprising a stress relaxation agent composed of silicone oil, wherein the stress relation agent is at least one compound selected from the group of compounds represented by formula (1):
wherein, in formula (1), X is independently CH3, C2H5, C3H7, C6H5, C10H7, C12H9, Y is independently CH3, C2H5, C3H7, C6H5, C10H7, C12H9, R is independently CH2, C2H4, C3H6, OCH2, OCH4, OC3H6, OC2H2, C2H2O, C3H4O, C4H6O, and n is 1-100. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die.
In accordance with yet another embodiment of the present disclosure, a method of fabricating a semiconductor package includes forming a first package by the following steps. A semiconductor die is placed on a carrier. An insulating encapsulant is formed on the carrier and surrounding the semiconductor die, wherein the insulating encapsulant is formed from a molding composition comprising a stress relaxation agent composed of silicone oil, wherein the stress relation agent is at least one compound selected from the group of compounds represented by formula (1):
wherein, in formula (1), X is independently CH3, C2H5, C3H7, C6H5, C10H7, C12H9, Y is independently CH3, C2H5, C3H7, C6H5, C10H7, C12H9, R is independently CH2, C2H4, C3H6, OCH2, OCH4, OC3H6, OC2H2, C2H2O, C3H4O, C4H6O, and n is 1-100. A redistribution layer is formed to be disposed on the insulating encapsulant and electrically connected to the semiconductor die, and the carrier is de-bonded.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
