Patent Application
20250006699
The exemplary embodiments described herein relate generally to semiconductor package structures and, more specifically, to semiconductor package structures employing bridge technologies to connect semiconductor chip stacks.
Heterogeneous integration (HI) with regard to semiconductor devices allows for the realization of high speed and high bandwidth communication between chips (for example, CPU, GPU, and memory). The modular nature of HI allows for the use of packaging technologies to combine discrete chips, which may be of various sizes.
Silicon bridge technology may be used with HI to connect various kinds of chips. For example, one type of silicon horizontal bridge technology is embedded multi-die interconnect bridging (EMIB), which provides an alternative solution to a silicon interposer and uses silicon only in areas where two dies are connected. Another type of silicon horizontal bridge technology is directed bonded heterogenous integration (DBHi), which involves the use of a silicon bridge directly bonded to and in between processor chips using copper pillars, thus allowing high-bandwidth low-latency low-power communication between the chips. Horizontal bridge technology may also be used in fan-out wafer-level packaging (FOWLP). Still other horizontal bridge technology for high-performance computing (HPC) applications may include 4-dimensional integration (4Di) bridging, which involves surface wiring to edges of memory chips and the joining of “cube memory chips” to packages.
However, current silicon bridge technology lacks the capabilities to enable various kinds of HI architectures, including chip stacks. It is also incapable of eliminating through-silicon vias (TSVs) in chip stacks since a bridge operates to deliver power, ground, and signal to chips stacks, and the use of TSVs detracts from such operation. Also, thermal management of the overall chip structure is less efficient in current silicon bridge technology.
In one exemplary aspect, a package structure comprises: a substrate having an upper surface; a first chip package positioned on the upper surface of the substrate, the first chip package comprising a first chip having a first integrated circuit connected to a first redistribution layer; a second chip package positioned on the upper surface of the substrate, the second chip package comprising a second chip having a second integrated circuit connected to a second redistribution layer; an orthogonal bridge positioned between the first chip package and the second chip package and having an interconnection to the first redistribution layer and the second redistribution layer; and a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge. The orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate.
The heat spreader may comprise at least one of aluminum, copper, or diamond. The first chip package and the second chip package may lack through-silicon vias. The interconnections of the orthogonal bridge to the first redistribution layer and the second redistribution layer may be solder interconnections. A plurality of first chips in the first chip package may be connected to each other via at least one of hybrid bonding, fusion bonding, or thermal compression bonding. A plurality of second chips in the second chip package may be connected to each other via at least one of hybrid bonding, fusion bonding, or thermal compression bonding. The plurality of first chips in the first chip package may be separated by first bumps. The plurality of second chips in the second chip package may be separated by second bumps. The orthogonal bridge may comprise one or more of silicon, silicon carbide, silicon dioxide, diamond, a silicon nitride, a glass, a dielectric material, a solder material, polymer, copper, tantalum, tantalum nitride, nickel, gold, aluminum nitride, indium, or combinations thereof.
In another exemplary aspect, a package structure comprises: a first chip stack comprising one or more first chips; a first bridge interconnected to a first lateral edge of the first chip stack; and a heat spreader positioned in direct contact with at least one of the first chip stack or the bridge. The first chip stack and a lower edge of the bridge are positioned on a planar surface of a substrate such that the first bridge extends orthogonal to the planar surface of the substrate.
The package structure may further comprise a second bridge having a lower edge positioned on the planar surface of the substrate, and the second bridge interconnected to a second lateral edge of the first chip stack. The package structure may further comprise a second chip interconnected to an upper edge of the first bridge and to an upper edge of the second bridge. The first bridge and the second bridge may be cube memory chips. The heat spreader may comprise at least one of aluminum, copper, or diamond. An interconnection of the first chip stack to the first bridge may be a solder interconnection. The first bridge may transport at least one of current or voltage to the first chip stack.
In another exemplary aspect, a method comprises: assembling a plurality of chips into a stack without through-silicon vias, each chip of the plurality of chips having a redistribution layer; bonding the plurality of stacked chips together; bonding the bonding and stacked chips to a bridge at lateral edges of the chips to interconnect the redistribution layers to the bridge; bonding the bonded and stacked chips and the bridge to a substrate; and attaching a heat spreader to the bonded and stacked chips. The bridge extends orthogonal to a planar surface of the substrate.
The plurality of chips may be assembled into a stack without through-silicon vias. The bonding of the plurality of stacked chips may be by at least one or hybrid bonding, fusion bonding, or thermal compression bonding. The method may further comprise underfilling space between the stacked chips.
The foregoing and other aspects of exemplary embodiments are made more evident in the following Detailed Description, when read in conjunction with the attached Drawing Figures, wherein:
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. All of the embodiments described in this Detailed Description are exemplary embodiments provided to enable persons skilled in the art to make or use the invention and not to limit the scope of the invention which is defined by the claims.
The exemplary embodiments described herein are directed to semiconductor packages in which bridges connect adjacently-positioned chip stacks, the bridges being positioned orthogonal to substrates on which the chip stacks are mounted. The chip stacks may comprise one or more chips or chiplets, each having one or more integrated circuits, and each integrated circuit having a redistribution structure.
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The orthogonal bridge 130 is located between or adjacent to the chip stacks 105, 110. Interconnections are fabricated at the lateral surfaces of each of the chip stacks 105, 110 with edges of the chips 120 in the chip stacks 105, 110 being bonded to the orthogonal bridge 130. The interconnections between the chip stacks 105, 110 and the orthogonal bridge 130 may be solder interconnections. The orthogonal bridge 130 is substantially perpendicular to the top surface of the substrate 115. In other example embodiments, one or more of the chip stacks 105, 110 may be bonded to another chip stack or to a silicon IP core.
In any embodiment, materials from which the orthogonal bridge 130 may be fabricated include, but are not limited to, silicon, silicon carbide, silicon dioxide, diamond, a silicon nitride, a glass, a dielectric material, a solder material, polymer, copper, tantalum, tantalum nitride, nickel, gold, aluminum nitride, indium, or combinations thereof.
In addition, the orthogonal bridge 130 may comprise a waveguide, a superconductor, a transistor, or a laser. The orthogonal bridge 130 may include a circuit separate from those on any of the connected chips 120. In addition to interconnections to the chip stacks 105, 110, interconnections may be made to a photonic integrated circuit (PIC) chip. Still further, the orthogonal bridge 130 may include a test channel for monitoring a known good die, thermal removal verification conditions, optical link verifications, optical link insertion loss, signal integrity, chip performance, chip functional performance metrics (for example, speed sort), voltage conditions (droop), chip functional signal integrity speed validation (PHY characterization for on module and/or off module interconnection), and clocking verification.
Still further, the orthogonal bridge 130 may be integrated into modules with a substrate 115 with organic packages, silicon packages, glass packages, ceramic packages, wafer-level or panel-level integration structures compatible with flip chip (FC) attach, ball grid array (BGA) attach, and/or hybrid or fusion bonding structures (Cu—Cu, Cu—Cu with silicon dioxide, silicon nitride, silicon oxygen nitride, dielectrics, and/or polymer dielectrics). Alternate metal-metal interconnections and dielectrics are also within the scope of the examples described herein.
A heat spreader 140 is located over and attached to the chip stacks 105, 110 and the orthogonal bridge 130 such that direct contact is maintained between edges of the chips 120 intermediately located in the chip stacks 105, 110 and between upper planar surfaces of the top chips 120 on top of the chip stacks 105, 110 at surfaces 142. Materials from which the heat spreader 140 may be fabricated include, but are not limited to, aluminum, copper, diamond, and the like. TSVs in the stacked chips 120 are eliminated, and the thickness of each stacked chip 120 can be thicker as compared to other architectures that do not employ orthogonal bridges, thus allowing for the contact area with the heat spreader to be larger. For example, a thickness of each chip 120 may be 400 micrometers (um). The heat spreader 140 (as well as other heat spreaders described below) provides for efficient thermal management in the semiconductor structure 100.
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Orthogonal bridges 130, 330, 530 (as well as cube memory chips) enable various kinds of HI architectures, including chip stacks. These bridges may be used with the architectures of modules using chiplet technologies, 2.XD technologies, as well as 3D technologies, with horizontal and vertical orientations. Because the orthogonal bridges operate to deliver power, ground, and signal to the chip stacks, the orthogonal bridges may obviate the need for TSVs in chip stacks. Furthermore, the orthogonal bridges as described herein may provide for voltage regulation, capacitance, inductance, magnetic inductance, resistance, or any computer user interface system application to multi-touch devices.
By the orthogonal bridges described in the embodiments disclosed herein, various examples of heterogenous integrations may be realized. For example, fabrication efficiencies may be improved, and lower cost opportunities may be presented in the manufacture of semiconductor architectures using orthogonal bridge technologies. Also, architecture efficiency may be improved overall in that opportunities are presented for the optional use of TSVs without a reduction in circuit area, and integrated thermal solutions may be presented for each chip. Additionally, wiring lengths may be shortened between chips.
In addition, orthogonal bridges may be formed using cube memory chips (for example, with suitable controllers and/or artificial intelligence (AI) accelerators). Combined with horizontal bridges, applications of HI become more flexible for many applications. Overall value is improved because HI may prove to be a key semiconductor packaging technology in the future.
In one aspect, a package structure comprises: a substrate having an upper surface; a first chip package positioned on the upper surface of the substrate, the first chip package comprising a first chip having a first integrated circuit connected to a first redistribution layer; a second chip package positioned on the upper surface of the substrate, the second chip package comprising a second chip having a second integrated circuit connected to a second redistribution layer; an orthogonal bridge positioned between the first chip package and the second chip package and having an interconnection to the first redistribution layer and the second redistribution layer; and a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge. The orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate.
The heat spreader may comprise at least one high temperature thermally conducting material such as aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof. The first chip package and the second chip package may lack through-silicon vias. The interconnections of the orthogonal bridge to the first redistribution layer and the second redistribution layer may be solder interconnections. A plurality of first chips in the first chip package may be connected to each other via at least one of hybrid bonding, fusion bonding, or thermal compression bonding. A plurality of second chips in the second chip package may be connected to each other via at least one of hybrid bonding, fusion bonding, or thermal compression bonding. The plurality of first chips in the first chip package may be separated by first bumps. The plurality of second chips in the second chip package may be separated by second bumps. The orthogonal bridge may comprise one or more of silicon, silicon carbide, silicon dioxide, diamond, a silicon nitride, a glass, a dielectric material, a solder material, polymer, copper, tantalum, tantalum nitride, nickel, gold, aluminum nitride, indium, or combinations thereof.
In another aspect, a package structure comprises: a first chip stack comprising one or more first chips; a first bridge interconnected to a first lateral edge of the first chip stack; and a heat spreader positioned in direct contact with at least one of the first chip stack or the bridge. The first chip stack and a lower edge of the bridge are positioned on a planar surface of a substrate such that the first bridge extends orthogonal to the planar surface of the substrate.
The package structure may further comprise a second bridge having a lower edge positioned on the planar surface of the substrate, and the second bridge interconnected to a second lateral edge of the first chip stack. The package structure may further comprise a second chip interconnected to an upper edge of the first bridge and to an upper edge of the second bridge. The first bridge and the second bridge may be cube memory chips. The heat spreader may comprise at least one high temperature thermally conducting material such as aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof. An interconnection of the first chip stack to the first bridge may be a solder interconnection. The first bridge may transport at least one of current or voltage to the first chip stack.
In another aspect, a method comprises: assembling a plurality of chips into a stack without through-silicon vias, each chip of the plurality of chips having a redistribution layer; bonding the plurality of stacked chips together; bonding the bonding and stacked chips to a bridge at lateral edges of the chips to interconnect the redistribution layers to the bridge; bonding the bonded and stacked chips and the bridge to a substrate; and attaching a heat spreader to the bonded and stacked chips. The bridge extends orthogonal to a planar surface of the substrate.
The plurality of chips may be assembled into a stack without through-silicon vias. The bonding of the plurality of stacked chips may be by at least one or hybrid bonding, fusion bonding, or thermal compression bonding. The method may further comprise underfilling space between the stacked chips.
In the foregoing description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be appreciated by one of ordinary skill of the art that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or processing steps may have been omitted or may have not been described in order to avoid obscuring the presented embodiments. It will be understood that when an element as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly” over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limiting in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical applications, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular uses contemplated.
