The present invention relates in general to integrated circuit packaging and more particularly to an improved process for fabricating an integrated circuit package, that includes unique features that allow gang testing of integrated circuit packages and etching to provide mold interlock.
According to well known prior art IC (integrated circuit) packaging methodologies, semiconductor dice are singulated and mounted using epoxy or other conventional means onto respective die pads (attach paddles) of a leadframe strip. Traditional QFP (Quad Flat Pack) packages incorporate inner leads which function as lands for wire bonding the semiconductor die bond pads. These inner leads typically require mold locking features to ensure proper positioning of the leadframe strip during subsequent molding to encapsulate the package. The inner leads terminate in outer leads that are bent down to contact a motherboard, thereby limiting the packaging density of such prior art devices.
In order to overcome these and other disadvantages of the prior art, the Applicants previously developed a Leadless Plastic Chip Carrier (LPCC). According to Applicants' LPCC methodology, a leadframe strip is provided for supporting up to several hundred devices. Singulated IC dice are placed on the strip die attach pads using conventional die mount and epoxy techniques. After curing of the epoxy, the dice are gold wire bonded to peripheral internal leads. The leadframe strip is then molded in plastic or resin using a modified mold wherein the bottom cavity is a flat plate. In the resulting molded package, the die attach pad (paddle) and leadframe inner leads are exposed. By exposing the bottom of the die attach pad, mold delamination at the bottom of the die attach pad is eliminated, thereby increasing the moisture sensitivity performance. Also, thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard. By exposing the leadframe inner leads, the requirement for mold locking features of outer leads is eliminated and no outer leads are necessary, thereby increasing device density and reducing package thickness over prior art methodologies. The exposed inner leadframe leads function as solder pads for motherboard assembly such that less gold wire bonding is required as compared to prior art methodologies, thereby improving electrical performance in terms of board level parasitics and enhancing package design flexibility over prior art packages (i.e. custom trim tools and form tools are not required). These and several other advantages of Applicants' own prior art LPCC process are discussed in Applicants' U.S. Pat. No. 6,229,200, issued May 8, 2001, the contents of which are incorporated herein by reference.
According to Applicants' U.S. Pat. No. 6,498,099, the contents of which are incorporated herein by reference, a localized etch process is provided for the improved manufacture of the LPCC IC package. The leadframe strip is subjected to a partial etch on one or both of the top and bottom surfaces in order to create a pattern of contact leads (pads) and a die attach pad (paddle). This method of manufacture provides many advantages including contact pads that stand off from the remainder of the package.
In Applicants' own U.S. patent application Ser. No. 09/802,678, the contents of which are incorporated herein by reference, a plate-up process is used to form contact pads and a die attach pad. The unique plate-up process results in columnar shaped contact pads with a “mushroom cap” or rivet-shaped top for mold interlocking to provide superior board mount reliability.
Further improvements in integrated circuit packaging are still desirable and are driven by industry demands for increased thermal and electrical performance and decreased size and cost of manufacture.
According to one aspect of the present invention, there is provided a process for fabricating an integrated circuit package. At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad. A carrier strip is laminated to the first side of the leadframe strip and a second side of the leadframe strip is selectively etched to thereby define a remainder of the die attach pad and the at least one row of contacts. A semiconductor die is mounted to the die attach pad, on the second side of the leadframe strip and the semiconductor die is wire bonded to ones of the contacts. The second side of the leadframe strip is encapsulated, including the semiconductor die and wire bonds, in a molding material. The carrier strip is removed from the leadframe strip and the integrated circuit package is singulated from a remainder of the leadframe strip.
Advantageously, the unique etch-back process results in mold interlocking features for better board mount reliability. Also, the mold interlocking features are provided by an etch-back process that results in decreased cost of manufacture as compared to plate-up processes.
In one aspect, the package is manufactured using a carrier strip that is laminated to the leadframe strip. Advantageously, the carrier strip provides increased rigidity and support for the leadframe strip during manufacture. In another aspect, the contacts of the leadframe strip are electrically isolated by etching prior to mounting the semiconductor die to the die attach pad. This permits gang testing of the individual units of the strip prior to singulation. Advantageously, package handling and testing time is reduced.
The present invention will be better understood with reference to the drawings and to the following description, in which:
Reference is first made to
The process for fabricating the integrated circuit package 20 will now be further described with reference to the Figures. Referring first to
Referring to
As shown in
The second side of the leadframe strip 22 is then selectively plated with a metal 38 that permits wire bonding thereto and acts as an etch resistant layer, using known selective plating techniques (
Next, the carrier strip 28 is prepared for laminating to the first side of the leadframe strip 22. The carrier strip 28 is made of any suitable metal, such as copper, and is plated with metal on both sides thereof, prior to lamination, as shown in the sectional side view of
Referring to
After lamination of the carrier strip 28 to the first side of the leadframe strip 22, the second side of the leadframe strip is selectively etched as shown in
The semiconductor die 30 is conventionally mounted by, for example, epoxy or other suitable means, to the die attach pad 24, on the second side of the leadframe strip 22. Wire bonds 32 are then bonded between the semiconductor die 30 and the contacts 26. The leadframe strip 22 is then molded in the molding material 34 using a modified mold with a bottom cavity being a flat plate, and subsequently cured (
Next, the carrier strip 28 is removed from the first side of the leadframe strip 22 by heating and pulling the carrier strip 28 from the leadframe strip 22 (
As stated above, the contacts 26 and die attach pad 24 are electrically isolated prior to singulating, thereby permitting gang testing of the individual units. Testing is then carried out on the unit prior to singulation (
Singulation of the individual unit from the full leadframe strip 22 is then performed either by saw singulation or by die punching (
Alternatives and variations to the above-described process are possible. Reference is made to
The present invention has been described by way of examples. Modifications and variations to the embodiments described herein may occur to those skilled in the art. For example, rather than using a pick and place technique, solder paste printing followed by known reflow technique is also possible. Other modifications and variations are also possible, all of which are within the sphere and scope of the present invention.
This is a continuation-in-part of U.S. patent application Ser. No. 10/765,192, filed Jan. 28, 2004, now U.S. Pat. No. 7,049,177 entitled Leadless Plastic Chip Carrier with Standoff Contacts and Die Attach Pad and a continuation-in-part of U.S. patent application Ser. No. 09/802,678, filed Mar. 9, 2001, now U.S. Pat. No. 6,933,594 which is a continuation-in-part of U.S. patent application Ser. No. 09/288,352, filed Apr. 8, 1999 now U.S. Pat. No. 6,498,099, issued Dec. 24, 2002, which is a continuation-in-part of U.S. patent application Ser. No. 09/095,803 filed Jun. 10, 1998, now U.S. Pat. No. 6,299,200, issued May 8, 2001.
Number | Name | Date | Kind |
---|---|---|---|
4530152 | Roche et al. | Jul 1985 | A |
4685998 | Quinn et al. | Aug 1987 | A |
5066831 | Spielerger et al. | Nov 1991 | A |
5293072 | Tsuji et al. | Mar 1994 | A |
5444301 | Song et al. | Aug 1995 | A |
5457340 | Templeton, Jr. et al. | Oct 1995 | A |
5710695 | Manteghi | Jan 1998 | A |
5777382 | Abbott et al. | Jul 1998 | A |
5900676 | Kweon et al. | May 1999 | A |
5976912 | Fukutomi et al. | Nov 1999 | A |
6001671 | Fjelstad | Dec 1999 | A |
6057601 | Lau et al. | May 2000 | A |
6081029 | Yamaguchi | Jun 2000 | A |
6093584 | Fjelstad | Jul 2000 | A |
6194786 | Orcutt | Feb 2001 | B1 |
6229200 | McLellan et al. | May 2001 | B1 |
6238952 | Lin | May 2001 | B1 |
6294830 | Fjelstad | Sep 2001 | B1 |
6306685 | Liu et al. | Oct 2001 | B1 |
6459163 | Bai | Oct 2002 | B1 |
6498099 | McLellan et al. | Dec 2002 | B1 |
6528877 | Ernst et al. | Mar 2003 | B2 |
6545347 | McLellan | Apr 2003 | B2 |
6585905 | Fan et al. | Jul 2003 | B1 |
6586677 | Glenn | Jul 2003 | B2 |
6635957 | Kwan et al. | Oct 2003 | B2 |
6683368 | Mostafazadeh | Jan 2004 | B1 |
6740961 | Mostafazadeh | May 2004 | B1 |
6777265 | Islam et al. | Aug 2004 | B2 |
6821821 | Fjelstad | Nov 2004 | B2 |
6841414 | Hu et al. | Jan 2005 | B1 |
6946324 | McLellan et al. | Sep 2005 | B1 |
6955942 | Kobayashi et al. | Oct 2005 | B2 |
6975038 | Mostafazadeh | Dec 2005 | B1 |
6989294 | McLellan et al. | Jan 2006 | B1 |
7033866 | Chow et al. | Apr 2006 | B2 |
20020074672 | Huang et al. | Jun 2002 | A1 |
20030015780 | Kang et al. | Jan 2003 | A1 |
20060157831 | Ano | Jul 2006 | A1 |
20060170081 | Gerber et al. | Aug 2006 | A1 |
Number | Date | Country |
---|---|---|
59-208756 | Nov 1984 | JP |
Number | Date | Country | |
---|---|---|---|
Parent | 10765192 | Jan 2004 | US |
Child | 11137973 | US | |
Parent | 09802678 | Mar 2001 | US |
Child | 10765192 | US | |
Parent | 09288352 | Apr 1999 | US |
Child | 09802678 | US | |
Parent | 09095803 | Jun 1998 | US |
Child | 09288352 | US |