This application claims benefit under 35 USC 119 of Taiwan Application No. 094135635, filed on Oct. 13, 2005.
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device with electroless plating metal connecting layer and a method for fabricating the same.
With progress of the semiconductor package technology, various kinds of packages for semiconductor devices have been developed. The method for packaging a semiconductor device mainly includes: mounting a semiconductor chip on a package substrate or a lead frame, electrically connecting the semiconductor chip to the package substrate or the lead frame, and packaging the semiconductor chip and the substrate or the lead frame with encapsulation material.
In a conventional semiconductor package structure, a semiconductor chip is first adhered to the top surface of a substrate. Then, a wire bonding or flip chip packaging is performed. Subsequently, a plurality of solder balls is implanted on the back side of the substrate for electrical connection. Although such a method increases the number of pins, several connecting interfaces are required, thereby increasing the fabrication costs.
However, to electrically connect a semiconductor chip to a circuit board, a bump forming process, a reflowing process and an underfill process are required, which not only increases fabrication steps and fabrication costs, but also decreases quality and reliability of the solder structures, thereby reducing quality of the electrical connection of final products.
Referring to
However, devices used for forming an UBM structure are expensive and accordingly increase the fabrication costs. Meanwhile, it is difficult to fabricate the metal bumps 12 with a certain height, especially in a fine-pitch circuit board with high density.
In light of the above drawbacks in the conventional technology, an objective of the present invention is to provide a semiconductor device with electroless plating metal connecting layer and a method for fabricating the same, by which an electroless plating metal connecting layer is formed on electrode pads of a semiconductor chip so as to facilitate electrical connection for the semiconductor chip embedded in a supporting board.
Another objective of the present invention is to provide a semiconductor device with electroless plating metal connecting layer and a method for fabricating the same, which can simplify the fabrication process and reduce the fabrication costs.
In accordance with the above and other objectives, the present invention proposes a method for fabricating a semiconductor device with electroless plating metal connecting layer, comprising the steps of: providing a supporting board with at least one cavity; receiving at least one semiconductor chip in the cavity, wherein, the semiconductor chip has an active surface with a plurality of copper electrode pads thereon and a non-active surface opposed to the active surface; forming an insulating protecting layer on the active surface of the semiconductor chip and forming a plurality of holes in the insulating protecting layer to expose the copper electrode pads; and forming an electroless plating metal connecting layer on the exposed copper electrode pads by electroless plating.
Subsequently, an insulating layer can be formed on the active surface of the semiconductor chip and on the supporting board. A circuit layer is formed on the insulating layer and conductive structures are formed in the insulating layer such that the circuit layer can be electrically connected to the electroless plating metal connecting layer by the conductive structures. A circuit build-up process can further be performed on the insulating layer and the circuit layer on the insulating layer to form a circuit build-up structure.
By the above fabrication method, a semiconductor device with electroless plating metal connecting layer is obtained, which comprises: a supporting board with at least one cavity; at least one semiconductor chip received in the cavity, wherein the semiconductor chip has an active surface with a plurality of copper electrode pads thereon and a non-active surface opposed to the active surface; an insulating protecting layer formed on the active surface of the semiconductor chip, which has a plurality of holes therein to expose the copper electrode pads; and an electroless plating metal connecting layer formed on the copper electrode pads. The semiconductor device further comprises an insulating layer formed on the active surface of the semiconductor chip and on the supporting board; a circuit layer formed on the insulating layer and electrically connected to the electroless plating metal connecting layer. A circuit build-up structure can further be formed on the insulating layer having the circuit layer.
The present invention utilizes an easy and efficient electroless plating process to directly form an electroless plating metal connecting layer on the copper electrode pads of the semiconductor chip. Accordingly, electrical connecting structure can be formed without the need of high-cost UBM fabrication process. In addition, since the electroless plating metal connecting layer made of such as copper, silver, gold or alloy thereof has a same property as the copper electrode pads, a preferred bonding effect can be obtained. Thus, the electrically connecting process of the semiconductor chip is simplified and easily practiced, the production yields are increased and the fabrication costs are reduced.
The present invention relates generally to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device with electroless plating metal connecting layer and a method for fabricating the same. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
A circuit build-up process can be performed subsequently according to a practical requirement so as to form a semiconductor package with multi-layer circuits and at least one embedded semiconductor chip.
Accordingly, as shown in
An insulating layer 26 is further formed on the active surface of the semiconductor chip 24 and on the supporting board 20, and filling the cavity 200 of the supporting board 20 in order to fix the semiconductor chip 24 to the supporting board 20. A circuit layer 28 is formed on the insulating layer 26 and a plurality of conductive structures 261 are formed in the holes 26a of the insulating layer 26 such that the circuit layer 28 can be electrically connected to the electroless plating metal connecting layer 25 on the copper electrode pads 241 of the semiconductor chip 24 by the conductive structures 261. A circuit build-up structure (not shown) can further be formed on the insulating layer and the circuit layer on the insulating layer.
Therefore, by utilizing an easy and efficient electroless plating process to directly form an electroless plating metal connecting layer on the copper electrode pads of the semiconductor chip, the present invention eliminates the need of forming UBM structures and bumps in the prior art, thereby reducing the fabrication costs. In addition, a preferred bonding effect can be obtained since the electroless plating metal connecting layer made of such as copper and the copper electrode pads have a same property.
Thus, the electrically connecting process of the semiconductor chip is simplified and easily practiced. Meanwhile, the present invention increases the production yields and reduces the fabrication costs.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
094135635 | Oct 2005 | TW | national |