Patent Application
20240203812
The present invention relates to a semiconductor device, and can be suitably used in, for example, a semiconductor device in which two semiconductor chips are resin-sealed.
A semiconductor package is manufactured by mounting a semiconductor chip on a die pad, electrically connecting pads of the semiconductor chip and leads with wires, and sealing them with a resin.
Here, there are disclosed techniques listed below.
Patent Document 1 discloses that a discharge occurs between a high-voltage terminal and a low-voltage terminal, which are exposed from a sealing body of a semiconductor device.
In a semiconductor device in which a first semiconductor chip and a second semiconductor chip are mounted on a first die pad and a second die pad, respectively, and in which the first semiconductor chip and the second semiconductor chip are resin-sealed, when a discharge occurs between the first die pad and the second die pad, which are exposed from a resin sealing body, a leakage current is generated between the first die pad and the second die pad. Given this leads to a deterioration in the performance of the semiconductor device, it is desired to be avoided the discharge.
Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.
According to one embodiment, a semiconductor device according to one embodiment, includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip mounted on the second chip mounting portion, a plurality of lead portions, and a sealing portion sealing them. The sealing portion has a first main surface and a second main surface opposite the first main surface. A groove portion is formed in the sealing portion at the first main surface. At the first main surface of the sealing portion, each of the first chip mounting portion and the second chip mounting portion is exposed from the sealing portion. At the first main surface of the sealing portion, the groove portion is formed between an exposed portion of the first chip mounting portion and an exposed portion of the second chip mounting portion.
In the following embodiments, when required for convenience, the description will be made by dividing into a plurality of sections or embodiments, but except when specifically stated, they are not independent of each other, and one is related to the modified example, detail, supplementary description, or the like of part or all of the other. In the following embodiments, the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.) is not limited to the specific number, but may be not less than or equal to the specific number, except for cases where the number is specifically indicated and is clearly limited to the specific number in principle. Furthermore, in the following embodiments, it is needless to say that the constituent elements (including element steps and the like) are not necessarily essential except in the case where they are specifically specified and the case where they are considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of components and the like, it is assumed that the shapes and the like are substantially approximate to or similar to the shapes and the like, except for the case in which they are specifically specified and the case in which they are considered to be obvious in principle, and the like. The same applies to the above numerical values and ranges.
Embodiments will be explained in detail on the basis of drawings. In all the drawings for explaining the embodiments, members having the same functions are denoted by the same reference numerals, and repetitive descriptions thereof are omitted. In the following embodiments, descriptions of the same or similar parts will not be repeated in principle except when particularly necessary.
In the drawings used in the embodiments, hatching may be omitted even in the case of cross-sectional view in order to make the drawings easier to see. Also, even in the case of a plan view, hatching may be used to make the drawing easier to see.
The construction of a semiconductor device PKG1 of the present embodiment will be described by referring to
It should be noted that
The semiconductor device PKG1 shown in
The semiconductor device PKG1 includes a die pad (chip mounting portion) DP1, DP2, a semiconductor chip CP1 mounted on the die pad DP1, a semiconductor chip CP2 mounted on the die pad DP2, a plurality of leads (lead portions) LD1, LD2, a plurality of bonding wires (hereinafter simply referred to as wires) BW1, BW2, BW3, and a sealing portion (sealing resin portion, sealing member) MR for sealing them.
The sealing portion MR is made of, for example, a resin material such as a thermosetting resin material, and may include fillers and the like. For example, the sealing portion MR can be formed using a filler-containing epoxy-resin or the like.
The die pad DP1, DP2 and the lead LD1, LD2 are made of an electrical conductor, and are preferably made of a metallic material such as copper (Cu) or a copper alloy. The die pad DP1, DP2 and the lead LD1, LD2 are preferably formed of the same material (the same metallic material) as each other, and thus it is easy to manufacture a lead frame in which the die pad DP1, DP2 and the lead LD1, LD2 are connected to each other, and thus it is easy to manufacture the semiconductor device PKG1 using the lead frame.
A part of the lead LD1, LD2 is sealed in the sealing portion MR, and the other part protrudes from the side surface of the sealing portion MR to the outside of the sealing portion MR. Hereinafter, a portion of each lead LD1, LD2 located in the sealing portion MR is referred to as an inner lead portion, and a portion of each lead LD1, LD2 located outside the sealing portion MR is referred to as an outer lead portion.
Note that the semiconductor device PKG1 of the present embodiment has a configuration in which a part (outer lead portion) of each lead LD1, LD2 protrudes from the side surface of the sealing portion MR, and will be described below based on this structure, but the structure is not limited to this structure, and for example, a structure in which each lead LD1, LD2 hardly protrudes from the side surface of the sealing portion MR and a part of each lead LD is exposed on the lower surface of the sealing portion MR may be adopted.
The semiconductor chip CP1 has a front surface CPla and a rear surface CP1b, which are main surfaces opposite to each other. A plurality of pad electrodes (hereinafter, simply referred to as “pads”) PD1a, PD1b are formed on the front CPla of the semiconductor chip CP1. The semiconductor chip CP2 has a front surface CP2a and a rear surface CP2b, which are main surfaces opposite to each other. A plurality of pad electrodes (hereinafter, simply referred to as “pads”) PD2a, PD2b are formed on the front CP2a of the semiconductor chip CP2.
The die pad DP1 is a chip mounting portion for mounting the semiconductor chip CP1. The die pad DP1 has a chip mounting surface DPla, which is a main surface on the side on which the semiconductor chip CP1 is mounted, and a back surface DP1b, which is an opposing main surface. The semiconductor chip CP1 is mounted on the chip mounting surface DPla of the die pad DP1 via a bonding material BD1 such that the back surface CP1b of the semiconductor chip CP1 faces the chip mounting surface DPla of the die pad DP1. That is, the back surface CP1b of the semiconductor chip CP1 is bonded to the chip mounting surface DP1a of the die pad DP1 via the bonding material BD1.
The die pad DP2 is a chip mounting portion for mounting the semiconductor chip CP2. The die pad DP2 has a chip mounting surface DP2a, which is a main surface on the side on which the semiconductor chip CP2 is mounted, and a back surface DP2b, which is an opposing main surface. The semiconductor chip CP2 is mounted on the chip mounting surface DP2a of the die pad DP2 via a bonding material BD2 such that the back surface CP2b of the semiconductor chip CP2 faces the chip mounting surface DP2a of the die pad DP2. That is, the back surface CP2b of the semiconductor chip CP2 is bonded to the chip mounting surface DP2a of the die pad DP2 via the bonding material BD2. Each of the bonding material BD1, BD2 is made of a conductive bonding material such as solder or silver paste.
The semiconductor device PKG1 includes a plurality of leads LD1, a plurality of leads LD2, a plurality of wires BW1, a plurality of wires BW2, and a plurality of wires BW3. The semiconductor chip CP1 includes a plurality of pads PD1a and a plurality of pads PD1b. The semiconductor chip CP2 includes a plurality of pads PD2a and a plurality of pads PD2b.
A plurality of pads PD1a of the semiconductor chip CP1 and a plurality of leads LD1 are electrically connected to each other via a plurality of wires BW1. That is, one end portion of both ends of each wire BW1 is connected to each pad PD1a of the semiconductor chip CP1, and the other end portion is connected to the inner lead portion of each lead LD1. A plurality of pads PD2a of the semiconductor chip CP2 and a plurality of leads LD2 are electrically connected to each other via a plurality of wires BW2. That is, one end portion of both ends of each wire BW2 is connected to each pad PD2a of the semiconductor chip CP2, and the other end portion is connected to the inner lead portion of each lead LD2. A plurality of pads PD1b of the semiconductor chip CP1 and a plurality of pads PD2b of the semiconductor chip CP2 are electrically connected to each other via a plurality of wires BW3. That is, one end of both ends of each wire BW3 is connected to each pad PD1b of the semiconductor chip CP1, and the other end thereof is connected to each pad PD2b of the semiconductor chip CP2. The respective wire BW1, BW2, BW3 are electrically conductive, in particular made of metallic material, for example gold wire.
The planar shape of the sealing portion MR is substantially rectangular, and has four sides, and in the cases of
Here, the X direction and the Y direction are directions intersecting with each other, and more specifically, directions orthogonal to each other. In addition, the Z direction is a direction perpendicular to the X direction and the Y direction, and therefore is a thickness direction of the sealing portion MR.
The sealing portion MR has a principal surface MRa and a principal surface MRb which are located opposite to each other. That is, the sealing portion MR has a main surface MRa, a main surface MRb opposite to the main surface MRa, and four side surfaces (specifically, two side surfaces substantially parallel to the X direction and two side surfaces substantially parallel to the Y direction) connecting the main surface MRa and the main surface MRb. The main surface MRa, MRb is substantially parallel to the X direction and the Y direction, and the Z direction is substantially perpendicular to the main surface MRa, MRb.
In the present embodiment, the sealing portion MR has a main surface MRa of upper surface, and the sealing portion MR has a main surface MRb of a lower surface. Therefore, when the semiconductor device PKG1 is mounted on a mounting substrate (corresponding to a mounting substrate PB1 to be described later) or the like, the mounting substrate is mounted with the main surface MRb of the sealing portion MR serving as a mounting surface and the main surface MRb of the sealing portion MR facing the mounting substrate.
The semiconductor chip CP1, CP2 and the plurality of wires BW1, BW2, BW3 are sealed in the sealing portion MR and are not exposed from the sealing portion MR. On the other hand, the die pad DP1, DP2 except the back surface DP1b, DP2b is sealed in the sealing portion MR and is not exposed from the sealing portion MR, but the back surface DP1 of the die pad DP1 and the back surface DP2b of the die pad DP2 are exposed from the main surface MRb of the sealing portion MR. In the main surface MRb of the sealing portion MR, the back surface DP1b, which is an exposed portion of the die pad DP1, and the back surface DP2b, which is an exposed portion of the die pad DP2, are spaced apart from each other by a predetermined distance in the Y-direction.
On the main surface MRb of the sealing portion MR, between the exposed portion (back surface DP1b) of the die pad DP1 and the exposed portion (back surface DP2b) of the die pad DP2, a groove portion (concave portion, recessed portion) TR of the sealing portion is formed. Specifically, in the main surface MRb of the sealing portion MR, the groove portion TR is formed along the X-direction so as to cross the region between the exposed portion (back surface DP1b) of the die pad DP1 and the exposed portion (back surface DP2b) of the die pad DP2. The main surface MRb of the sealing portion MR is a substantially flat surface except for the groove portion TR, but is locally recessed in the groove portion TR. The groove portion TR includes a bottom surface and both side walls (both side surfaces), and both side walls are substantially parallel to the X-direction.
The outer lead portions of the respective lead LD1, LD2 protrude from the side surface of the sealing portion MR to the outside of the sealing portion MR. The outer lead portions of the respective lead LD1, LD2 are bent toward the main surface MRb of the sealing portion. Specifically, the outer lead portions of the respective lead LD1, LD2 are bent so that the lower surface near the end portion of the outer lead portion is located on substantially the same plane as the lower surface (in this case, the main surface MRb) of the sealing portion MR. The outer lead portion of the lead LD1, LD2 functions as an external connecting terminal portion (external terminal) of the semiconductor device PKG1.
In a plan view, the die pad DP1 and the die pad DP2 face each other in the Y direction (adjacent to each other in the Y direction). However, the die pad DP1 and the die pad DP2 are not in contact with each other and are spaced apart from each other by a predetermined distance, and a part of the sealing portion MR is interposed between the die pad DP1 and the die pad DP2. Note that the plan view corresponds to a plan view when viewed in a plane substantially parallel to the main surface MRa of the sealing portion MR, the chip mounting surface DP1a of the die pad DP1, the chip mounting surface DP2a of the die pad DP2, the surface of the semiconductor chip CP1, or the surface of the semiconductor chip CP2.
Each of the planar shapes of the semiconductor chip CP1, CP2 is substantially rectangular and has four sides, and in
The planar dimension (planar area) of the semiconductor chip CP1 is smaller than the planar dimension (planar area) of the die pad DP1, and the semiconductor chip CP1 is included in the chip mounting surface DP1a of the die pad DP1 in plan view. Further, the planar dimension (planar area) of the semiconductor chip CP2 is smaller than the planar dimension (planar area) of the die pad DP2, and the semiconductor chip CP2 is included in the chip mounting surface DP2a of the die pad DP2 in plan view.
The height position of the die pad DP1 and the height position of the die pad DP2 are the same as each other. Therefore, the height position of the die pad DP1 on the chip mounting surface DP1a and the height position of the die pad DP2 on the chip mounting surface DP2a are the same as each other. In addition, the height position of the back surface DP1b of the die pad DP1 and the height position of the back surface DP2b of the die pad DP2 are the same as each other. The thickness of the die pad DP1 and the thickness of the die pad DP2 are the same as each other.
In the present application, when referring to the height position, the height position in the thickness direction of the sealing portion MR (Z direction), the side close to the main surface MRa of the sealing portion MR, the height is a high side, the side far from the main surface MRa of the sealing portion MR, the height is a low side.
Also, although the semiconductor device PKG of the present embodiment has a plurality of leads LD1 and a plurality of leads LD2, the distance P2 between the lead LD1 and the lead LD2 along the outer surface of the sealing portion MR is larger than the distance P1 between the die pad DP1 and the die pad DP2 (i.e., “P2>P1”). Here, the outer surface of the sealing portion MR is comprised of the main surface MRa and the main surface MRb of the sealing portion MR, and the side surface (four side surfaces when the planar shape of the sealing portion is rectangular) of the sealing portion MR. The distance P1 between the die pad DP1 and the die pad DP2 corresponds to a distance in a plan view. For example, when the die pad DP1 and the die pad DP2 are spaced apart from each other in the Y direction and are adjacent to each other, the distance P1 corresponds to the distance between the die pad DP1 and the die pad DP2 in the Y direction. Further, the closest distance P2 between the lead LD1 and the lead LD2 along the outer surface of the sealing portion MR corresponds to the distance (creepage distance) between the lead LD1 and the lead LD2, which are closest to each other in the plurality of leads LD1, LD2 included in the semiconductor device PKG. In case of
The first power (power for driving the circuitry in the semiconductor chip CP1) is supplied to the semiconductor chip CP1 in the semiconductor device PKG1 via the lead LD1 and the wire BW1. A second power (power for driving the circuitry in the semiconductor chip CP2) high than the first power is supplied to the semiconductor chip CP2 of the semiconductor device PKG1 via the lead LD2 and the wire BW2. A signal (control signal) for controlling the semiconductor chip CP2 (circuit in the semiconductor chip CP2) is supplied from the semiconductor chip CP1 in the semiconductor device PKG1 to the semiconductor chip CP2 via the wire BW3.
An exemplary manufacturing step of the semiconductor device PKG1 of the present embodiment will be described.
First, a lead frame having a lead LD1, LD2 and a die pad DP1, DP2 and a semiconductor chip CP1, CP2 are prepared. The semiconductor chip CP1, CP2 may be prepared first, the lead frame may be prepared first, or the semiconductor chip CP1, CP2 and the lead frame may be prepared together.
Next, a die bonding step is performed. Accordingly, the semiconductor chip CP1 is mounted on the die pad DP1 via the bonding material BD1 and bonded, and the semiconductor chip CP2 is mounted on the die pad DP2 via the bonding material BD2 and bonded. At this time, the semiconductor chip CP1 is mounted on the chip mounting surface DP1a of the die pad DP1 via the bonding material BD1 so that the back surface CP1b of the semiconductor chip DP1 faces the chip mounting surface DP1a of the die pad. Further, the semiconductor chip CP2 is mounted on the chip mounting surface DP2a of the die pad DP2 via the bonding material BD2 so that the back surface CP2b of the semiconductor chip DP2 faces the chip mounting surface DP2a of the die pad.
Next, a wire bonding step is performed. As a result, the plurality of pads PD1a of the semiconductor chip CP1 and the plurality of leads LD1 are electrically connected to each other via the plurality of wires BW1. Further, the plurality of pads PD2a of the semiconductor chip CP2 and the plurality of leads LD2 are electrically connected to each other via the plurality of wires BW2. Further, the plurality of pads PD1b of the semiconductor chip CP1 and the plurality of pads PD2b of the semiconductor chip CP2 are electrically connected to each other via the plurality of wires BW3.
Next, a molding step is performed to form a sealing portion MR. At this time, a portion corresponding to the groove TR is provided in the mold for forming the sealing part MR, so that the sealing part MR has the groove TR at the stage when the sealing part MR is formed. Alternatively, it is also possible to form the groove TR on the sealing portion MR by grinding such as dicing after forming the sealing portion MR having no groove TR in the molding step. The former (contrivance of the mold) can simplify the manufacturing step.
Next, the lead LD1, LD2 is cut from the frame of the lead frame.
Next, the lead LD1, LD2 is bent.
In this way, the semiconductor device PKG1 of present embodiment can be produced.
The semiconductor device PKG1 is mounted on the mounting substrate PB1 such that the main surface MRb of the sealing portion MR faces the mounting substrate PB1. Each of the lead LD1, LD2 of the semiconductor device PKG1 is electrically connected to and fixed to the terminal TEL of the mounting substrate PB1 via a conductive bonding material such as a solder SD. In
The present inventors have studied a configuration in which a semiconductor chip requiring high breakdown voltage (a high breakdown voltage chip, for example, a semiconductor chip on which a IGBT is formed) and a semiconductor chip that controls the high breakdown voltage chip and does not require high breakdown voltage (a low breakdown voltage chip, for example, a control IC chip) are mounted in one semiconductor device. Specifically, a die pad (high breakdown voltage die pad) on which a high breakdown voltage chip is mounted and a die pad (low breakdown voltage die pad) on which a low breakdown voltage chip is mounted are provided, respectively, and in consideration of the heat dissipation property of the high breakdown voltage chip that is likely to generate heat, it is studied to expose the two die pads (at least high breakdown voltage die pad) from the sealing body. The semiconductor chip CP1 corresponds to a high breakdown voltage chip, and the semiconductor chip CP2 corresponds to a low breakdown voltage chip.
The semiconductor device PKG101 of the examined example 1 shown in
According to studies by the present inventors, in the semiconductor device PKG101 of the examined example 1 shown in
Here, the power supplied to the semiconductor chip CP2 to drive the circuit in the semiconductor chip CP2 is higher (larger) than the power supplied to the semiconductor chip CP1 to drive the circuit in the semiconductor chip CP1. That is, the semiconductor chip CP2 is supplied with power high than the power supplied to the semiconductor chip CP1. Reflecting this, a higher potential difference may be generated between the die pad DP101 on which the semiconductor chip CP1 is mounted and the die pad DP102 on which the semiconductor chip CP2 is mounted. When the high-potential difference is generated, discharge (corona discharge, creeping discharge) may occur along the front surface (main surface MR101b) of the sealing portion MR101 between the back surface of the die pad DP101 exposed from the main surface MR101b of the sealing portion and the back surface of the die pad DP102.
For the semiconductor device PKG201 of the examined example 2 shown in
For the semiconductor device PKG201 of the examined example 2 shown in
However, in the semiconductor device PKG201 of the examined example 2 shown in
In addition, in the semiconductor device PKG201 of the examined example 2 shown in
In the semiconductor device PKG301 of the examined example 3 shown in
In the semiconductor device PKG301 of the examined example 3 shown in
However, in the semiconductor device PKG301 of the examined example 3 shown in
In case of the semiconductor device PKG401 of the examined example 4 shown in
In the semiconductor device PKG401 of the examined example 4 shown in
However, in the semiconductor device PKG401 of the examined example 4 shown in
The semiconductor device PKG of the present embodiment includes a semiconductor chip CP1, CP2, a die pad DP1, DP2 for mounting the semiconductor chip CP1, CP2, a plurality of lead portions LD1, LD2, a plurality of wires BW1, BW2, BW3, and a sealing portion MR for sealing them. The semiconductor chip CP1 is mounted on the chip mounting surface DP1a of the die pad DP1 via a bonding material BD1, and the semiconductor chip CP2 is mounted on the chip mounting surface DP2a of the die pad DP2 via a bonding material BD2. The plurality of pads PD1a of the semiconductor chip CP1 and the plurality of lead portions LD1 are electrically connected to each other via a plurality of wires BW1, and the plurality of pads PD2a of the semiconductor chip CP2 and the plurality of lead portions LD2 are electrically connected to each other via a plurality of wires BW2. The plurality of pads PD1b of the semiconductor chip CP1 and the plurality of pads PD2b of the semiconductor chip CP2 are electrically connected to each other via the plurality of wires BW3.
One of the main features of present embodiment is that, from the main surface MRb of the sealing portion MR, the back surface DP1b of the die pad DP1 and the back surface DP2b of the die pad DP2 are respectively exposed, and the groove portion TR of the sealing portion MR is formed between the back surface DP1b of the die pad DP1 and the back surface DP2b of the die pad DP2 in the main surface MRb of the sealing portion MR. In the main surface MRb of the sealing portion MR, the groove portion TR is formed so as to cross a region between the back surface DP1b of the die pad DP1 and the back surface DP2b of the die pad DP2.
In the present embodiment, since the sealing portion MR has the main surface MRb exposed to each back surface DP1, DP2 of the die pad DP1b, DP2b, heat generated in CP1, CP2 of the semiconductor chip is easily released from the die pad to the outside of the semiconductor device PKG1. In particular, the semiconductor chip CP2 has a larger heat generation value than the semiconductor chip CP1 because the semiconductor chip CP2 is supplied with a larger power than the power supplied to the semiconductor chip CP1. Therefore, the temperature of the semiconductor chip CP2 and the die pad DP2 on which the semiconductor chip is mounted increases with the heat generation of the semiconductor chip CP2, but the die pad DP2 is exposed from the sealing portion MR having a lower thermal conductivity, so that the heat of the die pad DP2 is easily conducted to the outside of the semiconductor device PKG1. As a consequence, the performance of the semiconductor device PKG1 can be improved because the temperature increasing of the semiconductor chip CP1, CP2 (in particular, the semiconductor chip CP2) when the semiconductor device PKG1 is operated can be suppressed.
Further, in the present embodiment, in the main surface MRb of the sealing portion MR, it is possible to suppress or prevent the occurrence of a discharge between the back surface DP1b of the die pad DP1, which is exposed from the sealing portion MR at the main surface MRb of the sealing portion MR, and the back surface DP2b of the die pad DP2, which is exposed from the sealing portion MR at the main surface MRb of the sealing portion MR, by forming the groove TR in the sealing portion MR between the back surface DP1b of the die pad DP1 and the back surface DP2b of the die pad DP2. The reason for this will be described below.
In the semiconductor device PKG101 of the examined example 1 shown in
On the other hand, in the semiconductor device PKG1 of present embodiment, the creepage distance between the exposed portion (back surface DP1b) of the die pad DP1 and the exposed portion (back surface DP2b) of the die pad DP2 in the main surface MRb of the sealing portion MR is increased by the presence of the trench TR. Here, the creepage distance corresponds to a distance along the surface of the sealing portion MR interposed between the die pad DP1, DP2.
In the semiconductor device PKG of present embodiment, the creepage distance between the exposed portion (back surface DP1b) of the die pad DP1 and the exposed portion (back surface DP2b) of the die pad DP2 at the main surface MRb of the sealing portion MR is expressed as L1. In the semiconductor device PKG101 of the examined example 1 shown in
When a discharge occurs between the exposed portions of the die pad DP1, DP2 on the main surface MRb of the sealing portion MR, the length of the discharge path is approximately equal to the creepage distance L1 between the exposed portions of the die pad DP1, DP2. Therefore, as the creepage distance L1 increases, the length of the discharge path increases, and discharge is less likely to occur between the exposed portions of the die pad DP1, DP2. When the groove TR is formed, when the discharge occurs between the exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2 in the main surface MRb of the sealing portion MR, since the discharge path will include both side walls and the bottom surface of the groove TR, as compared with the case where the groove TR is not formed, the discharge path becomes longer, consequently, the exposed portions of the die pad DP1, DP2 (back surface DP1b, DP2b) discharge hardly occurs between. Therefore, as in the present embodiment, in the main surface MR of the sealing portion, in the main surface MRb of the sealing portion DP1b, DP2b, it is possible to suppress or prevent the occurrence of a discharge between exposed portions (back surface DP1, DP2) of the die pad DP1, DP2 on the main surface MR of the sealing portion MR by forming the groove portion TR of the sealing portion between exposed portions (back surface DP1b, DP2b) of the die pad OOG.
Further, in the present embodiment, since the groove TR is provided on the main surface MRb of the sealing portion MR, it is possible to increase the creepage distance between the exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2 on the main surface MRb of the sealing portion MR without increasing the distance between the die pad DP1, DP2. Therefore, the planar dimension (planar area) of the semiconductor device PKG1 can be suppressed. In addition, it is possible to prevent or prevent the wire BW3 from contacting each other when the sealing portion MR is formed.
Further, in the main surface MRb of the sealing portion MR, the groove portion TR is formed so as to cross a region between the back surface DP1b of the die pad DP1 and the back surface DP2b of the die pad DP2 (see
Further, in the main effect MRb of the sealing portion MR, the groove portion TR may not reach the side surface of the sealing portion DP1 because it is possible to suppress or prevent a discharge between the exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2 on the main surface MRb of the sealing portion MR as long as it crosses the region between the back surface DP1b of the die pad MR and the back surface DP2b of the die pad DP2. However, it is more preferable that the groove portion TR reaches both side surfaces (both side surfaces located on opposite sides) of the sealing portion MR, so that the groove portion TR of the sealing portion MR can be easily formed, and the discharge-suppressing effect can also be enhanced.
Further, as the depth D1 of the trench TR is increased, the creepage distance between the exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2 in the main surface MRb of the sealing portion MR is increased, so that a discharge is less likely to occur between the exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2. Therefore, the depth TR of the sealing portion MR in the groove D1 is preferably made deeper (larger) to some extent, and in this viewpoint, the depth D1 of the groove TR is preferably larger the respective thicknesses of the die pad DP1, DP2. That is, in the thickness direction (Z direction) of the sealing portion MR, the height position of the bottom surface of the trench TR is preferably higher than each of the chip mounting surface DP1a of the die pad DP1 and the chip mounting surface DP2a of the die pad DP2. Further, in the thickness direction (Z direction) of the sealing portion MR, it is more preferable that the height position of the bottom surface of the trench TR is higher than the central of the thickness of the semiconductor chip CP1, CP2.
On the other hand, if the groove TR is too deep, the groove TR may adversely affect the wire BW3. The wire BW3 connects the pad PD1b of the semiconductor chip CP1 and the pad PD2b of the semiconductor chip CP2, but it is possible to avoid the risk that the groove TR adversely affects the wire BW3 if the height position of the bottom surface of the groove TR is lower than the surface CPla of the semiconductor chip CP1 and the surface CP1 of the semiconductor chip. Therefore, the height position of the bottom surface of the trench TR is preferably lower than each of the surface CPla of the semiconductor chip CP1 and the surface CP2a of the semiconductor chip CP2.
Therefore, it is preferable that the height position of the bottom surface of the trench TR is higher than the respective chip mounting surface DP1a, DP2a of the die pad DP1, DP2 and lower than the respective front surface CPla, CP2a of the semiconductor chip CP1, CP2. Accordingly, it is possible to efficiently suppress or prevent a discharge between exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2 on the main surface MRb of the sealing portion MR while accurately preventing the forming of the trench TR from adversely affecting the wire BW3.
In addition, a discharge may occur beyond the groove TR if the width W1 of the groove TR (see
In the semiconductor device PKG1 of the present embodiment, the height position of the die pad DP1 and the height position of the die pad DP2 are the same in the thickness direction (Z direction) of the sealing portion MR. Therefore, it is easy to perform the wire bonding step at the time of manufacturing the semiconductor device PKG1. That is, in the wire bonding step, although it is necessary to connect each wire BW1, BW2, BW3 with each pad of each semiconductor chip CP1, CP2 mounted on each die pad DP1, DP2 while each die pad DP1, DP2 is supported, it is easy to support each die pad DP1, DP2 because the height positions of each die pad DP1, DP2 are the same as each other. Therefore, the semiconductor device PKG1 of the present embodiment facilitates the process control of the wire bonding step at the time of manufacturing. In addition, the manufacturing yield of the semiconductor device PKG1 can be improved, and the manufacturing cost of the semiconductor device PKG1 can be suppressed.
Also, in the semiconductor device PKG1 of the present embodiment, the lead LD1 and the lead LD2 along the outer surface of the sealing portion MR have a closest distance P2 larger than (i.e., “P2>P1”) a distance P1 between the die pad DP1 and the die pad DP2. Unlike present embodiment, there is a concern that creeping discharge (discharge along the outer surface of the sealing portion MR) occurs between the adjacent lead LD1 and the lead LD2 when the closest distance LD1 and the lead LD2 along the outer surface of the sealing portion P2 is smaller than the distance P1 between the die pad DP1 and the die pad DP2 (that is, when the distance is “P2<P1”). In contrast, in present embodiment, creeping a discharge is less likely to occur between the lead LD1 and the lead MR because the lead LD1 and the lead LD2 closest distance P2 along the outer surface of the sealing portion LD2 are larger than the distance P2 between the die pad DP1 and the die pad DP2 (i.e., MR). With respect to the die pad DP1 and the die pad DP2 in which creeping discharge is feared, creeping discharge between the die pad DP1 and the die pad DP2 can be suppressed or prevented by providing the trench MR the sealing portion with the trench TR as described above. For this reason, present embodiment is particularly useful when the closest distance P2 between the lead LD1 and the lead LD2 along the outer surface of the sealing portion MR is larger than the distance P1 between the die pad DP1 and the die pad DP2 (i.e., in “P2>P1”), and the same applies to the following embodiments 2˜5.
The construction of a semiconductor device PKG2 of the present embodiment 2 will be described by referring to
The semiconductor device PKG2 according to the embodiment 2 will be described below with a focus on the difference between the semiconductor device PKG1 of the embodiment 1 and the semiconductor device PKG2 of the embodiment 2.
In the semiconductor device PKG2 of the present embodiment 2, the groove TR is not formed on the main surface MRb of the sealing portion MR. Instead, in the present embodiment 2, the sealing portion MR is formed on the main surface MRb of the sealing portion MR at a position between the die pad DP1 and the die pad DP2 in a plan view with a step DS. That is, the main surface MRb of the sealing portion MR is constituted by a flat surface MRb1, a flat surface MRb2, and a step (step surface) DS connecting them, and the step DS is located at the boundary between the flat surface MRb1 and the flat surface MRb2. The distance between the surface MRb2 and the main surface MRa of the sealing portion MR (that is, the thickness of the sealing portion MR in the surface MRb2) is larger than the distance between the surface MRb1 and the main surface MRa of the sealing portion MR (that is, the thickness of the sealing portion MR in the surface MRb1). Each of the surface MRb1, MRb2 is a flat surface substantially parallel to the X direction and the Y direction. As in the embodiment 1, in the present embodiment 2, the main surface MRa of the sealing portion MR is a flat surface (more specifically, a flat surface substantially parallel to the X direction and the Y direction).
In a plan view, the level difference DS of the sealing portion MR is formed so as to cross the region between the die pad DP1 and the die pad DP2. Specifically, in a plan view, the die pad DP1 and the die pad DP2 are spaced apart from each other in the Y direction, and the sealing portion MR has a step DS extending in the X direction so as to cross the region between the die pad DP1 and the die pad DP2. Therefore, the level difference DS is substantially parallel to the X-direction. In
That is, in the present embodiment 2, the die pad DP2 is sealed in the sealing portion MR except for the back surface DP2b, and is not exposed from the sealing portion MR, but the embodiment 1 is the same in that the back surface DP2 of the die pad DP2 is exposed from the main surface MRb of the sealing portion MR. However, unlike the embodiment 1 described above, in the present embodiment 2, the die pad DP1 is also covered with the sealing portion MR on the back surface DP2b, so that the die pad DP2 is not exposed from the sealing portion MR. However, in the present embodiment 2, among the surface MRb1, the surface MRb2, and the level difference DS constituting the main surface MRb of the sealing portion MR, the back surface DP2 of the die pad DP2 is exposed from the surface MRb2. In present embodiment 2, the die pad DP1 is enclosed in a plane MRb1 in a plan view, and a sealing portion MR exists between the plane MRb1 and the back surface DP2 of the die pad DP2.
Similarly to the embodiment 1, in the present embodiment 2, the height position of the die pad DP1 and the height position of the die pad DP2 are the same as each other. Therefore, the height position of the die pad DP1 on the chip mounting surface DP1a and the height position of the die pad DP2 on the chip mounting surface DP2a are the same as each other. In addition, the height position of the back surface DP1b of the die pad DP1 and the height position of the back surface DP2b of the die pad DP2 are the same as each other. The thickness of the die pad DP1 and the thickness of the die pad DP2 are the same as each other.
In addition, in the above embodiment 1, the outer lead portions of the respective lead LD1, LD2 are bent toward the main surface MRb of the sealing portion, but in the present embodiment 2, the outer lead portions of the respective lead LD1, LD2 are bent toward the main surface MRa of the sealing portion. Specifically, the outer lead portions of the respective lead LD1, LD2 are bent so that the lower surface near the end portion of the outer lead portion is located on substantially the same plane as the main surface MRa of the sealing portion MR.
Therefore, in the present embodiment 2, the sealing portion MR has a main surface MRb of upper surface, and the sealing portion MR has a main surface MRa of a lower surface. When the semiconductor device PKG2 is mounted on a mounting substrate or the like, the semiconductor device PKG2 is mounted on the mounting substrate so that the main surface MRa of the sealing part MR serves as the mounting surface and the main surface MRa of the sealing part MR faces the mounting substrate PB.
Other configurations of the semiconductor device PKG2 of the present embodiment 2 are substantially the same as those of the semiconductor device PKG1 of the present embodiment 2, and therefore, repeated explanation thereof will be omitted here.
The manufacturing step of the semiconductor device PKG2 of the present embodiment 2 is different from that of the present embodiment 1 in the following points.
That is, by performing the molding step, to form a sealing portion MR, the sealing portion MR is provided with a portion corresponding to the level difference DS in the mold for forming the sealing portion MR so that the sealing portion MR has a step DS at the stage where the sealing portion is formed. Alternatively, it is also possible to form a step DS on the sealing portion MR by grinding or polishing after forming the sealing portion MR having no step DS in the molding step. The former (contrivance of the mold) can simplify the manufacturing step.
In addition, in the present embodiment 2, the bending direction in bending the lead LD1, LD2 is opposite to the bending direction in the embodiment 1.
As shown in
In
In the semiconductor device PKG2 of present embodiment 2, the back surface DP2b of the die pad DP2 is exposed from the main surface MRb of the sealing portion MR, but the back surface DP1b of the die pad DP1 is not exposed. Since one of the die pad DP1, DP2 (die pad DP1) is not exposed from the sealing portion MR (back surface MRb of the semiconductor chip CP1), no discharge (corona discharge, creeping discharge) occurs between the die pad DP1 and the die pad DP2 even if a high potential difference occurs between the die pad DP1 on which the semiconductor chip CP2 is mounted and the die pad OOI on which the semiconductor chip is mounted. In addition, in the semiconductor device PKG2 of the present embodiment 2, the back surface of the semiconductor chip CP1 on which the semiconductor chip CP2 having a larger calorific value than that of the semiconductor chip is mounted is exposed from the main surface MRb of the sealing portion MR, so that the heat generated in the semiconductor chip CP2 is easily emitted to the outside of the semiconductor device PKG2 from the die pad DP2.
In the semiconductor device PKG2 of present embodiment 2, the height position of the die pad DP1 and the height position of the die pad DP2 are the same in the thickness direction (Z direction) of the sealing portion MR. Therefore, it is easy to perform the wire bonding step at the time of manufacturing the semiconductor device PKG2. That is, in the wire bonding step, the die pad DP1, DP2 is easily supported because the wire CP1, CP2 needs to be connected to the pad of the semiconductor chip mounted on the die pad BW1, BW2, BW3 while the die pad DP1 is supported, but the height positions of the die pad CP1, CP2 and the die pad DP2 are the same. Therefore, the semiconductor device PKG2 of the present embodiment 2 facilitates the process control of the wire bonding step at the time of manufacturing. In addition, the manufacturing yield of the semiconductor device PKG2 can be improved, and the manufacturing cost of the semiconductor device PKG2 can be suppressed.
According to the present embodiment 2, it is possible to accurately obtain a configuration in which the back surface MR of the die pad MRb is not exposed, although the back surface DP2b of the die pad DS is exposed from the main surface MRb of the sealing portion MR even if the height position of the die pad DP1 and the height position of the die pad DP2 are the same as each other by providing the level difference DP2 on the main surface DP1b of the sealing portion. That is, by using the level difference MR of the sealing portion DS, the structure pad DP1 is not exposed from the sealing portion DP2, but the back surface DP2b of the die pad DP1 is exposed from the main surface MRb of the sealing portion.
In the semiconductor device PKG2 of the present embodiment 2, the outer lead portions of the respective lead LD1, LD2 are bent toward the main surface MRa of the sealing portion MR. Reflecting this, as shown in
The construction of a semiconductor device PKG3 of the present embodiment 3 will be described referring to
Note that
The semiconductor device PKG3 according to the embodiment 3 will be described below with a focus on the difference between the semiconductor device PKG1 of the embodiment 1 and the semiconductor device PKG3 of the embodiment 3.
In the semiconductor device PKG3 of the present embodiment 3, the groove TR is not formed on the main surface MRb of the sealing portion MR. Therefore, in present embodiment 3, the main surface MRb of the sealing portion MR is a flat surface (more specifically, a flat surface substantially parallel to the X direction and the Y direction). As in the embodiment 1, in present embodiment 3, the main surface MRa of the sealing portion MR is a flat surface (more specifically, a flat surface substantially parallel to the X direction and the Y direction).
In the semiconductor device PKG3 of the present embodiment 3, the die pad DP1 integrally includes the thick portion D1a and the thin portion Dlb thinner than the thick portion D1a. Further, the die pad DP2 integrally includes a thick portion D2a and a thin portion D2b thinner than the thick portion D2a. The thick portion D1a is a portion having a large thickness in the die pad DP1, and the thin portion D1b is a portion having a small thickness in the die pad DP1. The thick portion D2a is a portion having a large thickness in the die pad DP2, and the thin portion D2b is a portion having a small thickness in the die pad DP2.
The chip mounting surface DP1a of the die pad DP1 and the chip mounting surface DP2a of the die pad DP2 are flat surfaces (more specifically, flat surfaces substantially parallel to the X direction and the Y direction). The back surface DP1b of the die pad DP1 has a step at a boundary between the thick portion D1a and the thin portion D1b. The thick portion D1a has a substantially uniform thickness, the thin portion D1b has a substantially uniform thickness, and the thickness of the thin portion D1b is smaller than the thickness of the thick portion D1a. The back surface DP2b of the die pad DP2 has a step at a boundary between the thick portion D2a and the thin portion D2b. The thick portion D2a has a substantially uniform thickness, the thin portion D2b has a substantially uniform thickness, and the thickness of the thin portion D2b is smaller than the thickness of the thick portion D2a.
From the main surface MRb of the sealing portion MR, the thick portion DP1 of the die pad D2b and the thick portion D2a of the die pad DP2 are exposed, and the thin portion D1b of the die pad DP1 and the thin portion DP1 of the die pad MR are not exposed from the main surface MRb of the sealing portion.
That is, in the present embodiment 3, the die pad DP1 except the back surface DP1b in the thick portion D1a is sealed with the sealing portion MR and is not exposed from the sealing portion MR, but the back surface DP1b in the thick portion D1a of the die pad DP1 is exposed from the sealing portion MR at the main surface MRb of the sealing portion MR. Further, the die pad DP2 except the back surface DP2b in the thick portion D2a is sealed with the sealing portion MR and is not exposed from the sealing portion MR, but the back surface DP2b in the thick portion D2a of the die pad DP2 is exposed from the sealing portion MR at the main surface MRb of the sealing portion MR. Since the back surface DP1b in the thin portion D1b of the die pad DP1 and the back surface DP2b in the thin portion D2b of the die pad DP2 are covered with the sealing portion MR, they are not exposed from the sealing portion MR at the main surface MRb of the sealing portion MR.
Also, in the present embodiment 3, the height position of the die pad DP1 and the height position of the die pad DP2 are the same as each other. Therefore, the height position of the die pad DP1 on the chip mounting surface DP1a and the height position of the die pad DP2 on the chip mounting surface DP2a are the same as each other. In addition, the height position of the back surface DP1b in the thick portion D1a of the die pad DP1 and the height position of the back surface DP2b in the thick portion D2a of the die pad DP2 are the same as each other. The thickness of the thick portion D1a of the die pad DP1 and the thickness of the thick portion D2a of the die pad DP2 are the same as each other. When the thickness of the thick portion D1a of the die pad DP1 and the thickness of the thick portion D2a of the die pad DP2 are the same, the semiconductor device PKG3 can be easily manufactured using the lead frame. Further, in
The die pad DP1 and the die pad DP2 are spaced apart from each other in the Y direction, but the thin portion D1b of the die pad DP1 and the thin portion D2b of the die pad DP2 face each other in the Y direction. That is, in the die pad DP1, the thick portion D1a and the thin portion D1b are adjacent to each other in the Y-direction, the thin portion D1b is located on the side close to the die pad DP2, and the thick portion D1a is located on the side far from the die pad DP2. Further, in the die pad DP2, the thick portion D2a and the thin portion D2b are adjoined in the Y-direction, the thin portion D2b is located on the side close to the die pad DP1, and the thick portion D2a is located on the side far from the die pad DP1. That is, in plan view, between the thick portion D1a of the die pad DP1 and the thick portion D2a of the die pad DP2, the thin portion D1b of the die pad DP2 and the thin portion D2b of the die pad are disposed.
The semiconductor chip CP1 is mounted on the die pad DP1 via a bonding material BD1 so as to stride over the thick portion D1a and the thin portion D1b. Therefore, a thick portion D1a and a thin portion D1b of the die pad DP1 exist below the semiconductor chip CP1. That is, the semiconductor chip CP1 has a portion overlapping the thick portion D1a and a portion overlapping the thin portion D1b in plan view. The semiconductor chip CP2 is mounted on the die pad DP2 via a bonding material BD2 so as to stride over the thick portion D2a and the thin portion D2b. Therefore, a thick portion D2a and a thin portion D2b of the die pad DP2 exist below the semiconductor chip CP2. That is, the semiconductor chip CP2 has a portion overlapping the thick portion D2a and a portion overlapping the thin portion D2b in plan view.
Other configurations of the semiconductor device PKG3 of the present embodiment 3 are substantially the same as those of the semiconductor device PKG1 of the present embodiment 1, and therefore, repeated explanation thereof will be omitted here.
The manufacturing step of the semiconductor device PKG3 of the present embodiment 3 is different from that of the present embodiment 1 in the following points.
That is, a lead frame having a lead LD1, LD2 and a die pad DP1, DP2 is prepared, wherein the die pad DP1 has a thick portion D1a and a thin portion D1b, and the die pad DP2 has a thick portion D2a and a thin portion D2b. For example, a thin portion D1b, D2b that is relatively thinner than the thick portion D1a, D2a can be formed by, for example, half-etching a lead frame (or a metallic plate for forming a lead frame) from the back side. When the thickness of the thin portion D1b of the die pad DP1 and the thickness of the thin portion D1b of the die pad are the same as each other, the processing of the lead frame becomes easy.
In the present embodiment 3, in the sealing portion MR forming step, the groove portion TR may not be formed on the sealing portion MR. In this respect, the manufacturing step can be simplified.
As shown in
In case of
In the semiconductor device PKG3 of the embodiment 3, since the thick portion D1a (back surface) of the die pad DP1 and the thick portion D2a (back surface) of the die pad DP2 are exposed from the sealing portion MR at the mains surface MRb of the sealing portion MR, the heat generated in the semiconductor chip CP1, CP2 is easily emitted to the outside of the semiconductor device PKG1. As a consequence, it is possible to suppress an increase in the temperature of the semiconductor chip CP1, CP2 (particularly, semiconductor chip CP2) when the semiconductor device PKG1 is operated, and thus it is possible to improve the performance of the semiconductor device PKG3.
In addition, in the present embodiment 3, the die pad DP1 has a thick portion D1a and a thin portion D1b, and the die pad DP2 has a thick portion D2a and a thin portion D2b. The thin portion D1b of the die pad DP1 and the thin portion DP1b of the die pad DP2 face each other, and the thin portion D2b of the die pad MR is not exposed from the main surface MRb of the sealing portion MR and the thick portion D1a, D2a of the die pad DP1, DP2 is exposed, respectively, and from the main surface MR of the sealing portion. Accordingly, it is possible to suppress or prevent a discharge from occurring between exposed portions of the die pad DP1, DP2 on the main surface MRb of the sealing portion MR. The reason for this will be described below.
When the semiconductor device PKG3 of the present embodiment 3 is compared with the semiconductor device PKG101 of the examined example 1 shown in
Here, the distance L3 illustrated in
In the present embodiment 3, it is possible to increase the distance (creepage distance) between the exposed portions of the die pads DP1, DP2 at the main surface MRb of the sealing portion MR by arranging the thin portions D1b, D2b of the die pads DP1, DP2 next to each other and causing the main surface MRb of the sealing portion MR to expose the thick portion D1a, D2a of the die pad DP1, DP2 but not expose the thin portion D1b, D2b. As the distance (creepage distance) between the exposed portions of the die pad MR on the main surface MRb of the sealing portion MR is increased, a discharge is less likely to occur between the exposed portions of the die pad DP1, DP2 on the main surface MRb of the sealing portion. In the present embodiment 3, it is possible to suppress or prevent the occurrence of a discharge between exposed portions (back surface DP1, DP2) of the die pad DP1, DP2 on the main surface MRb of the sealing portion MR by causing the thin portions D1b, D2b of the die pad DP1b, DP2b to face each other and preventing the thin portion D1b, D2b of the die pad DP1, DP2 from being exposed on the main surface MRb of the sealing portion MR.
Further, in present embodiment 3, even if the distance (distance L3) between the die pad DP1, DP2 is not increased, the creepage distance (distance L4) between the exposed portions of the die pad DP1, DP2 on the main surface MRb of the sealing portion MR can be increased. Therefore, the planar dimension (planar area) of the semiconductor device PKG3 can be suppressed. In addition, it is possible to prevent or prevent the wire BW3 from contacting each other when the sealing portion MR is formed.
Further, in present embodiment 3, the semiconductor chip CP1 is mounted on the thick portion D1a of the die pad DP1 and the thin portion D1b via the bonding material BD1, and the semiconductor chip CP2 is mounted on the thick portion D2a and the thin portion DP2 of the die pad via the bonding material BD2. Therefore, the semiconductor chip CP1 has a portion overlapping the thick portion D1a and a portion overlapping the thin portion D1b in a plan view, and the semiconductor chip CP2 has a portion overlapping the thick portion D2a and a portion overlapping the thin portion D2b in a plan view.
Unlike present embodiment, it is assumed that the semiconductor chip CP1 is mounted only on the thick portion D1a of the die pad DP1, the semiconductor chip CP1 does not have a portion that overlaps the thin portion D1b in a plan view, and the semiconductor chip CP2 does not have a portion that overlaps the thin portion D2b in a plan view, and the semiconductor chip D1a is mounted only on the thick portion D2a of the die pad DP2. In this case, since the thin portion D1b, DP2b of the die pad DP1, DP2 does not contribute to the mounting area of the semiconductor chip CP1, CP2, it can be eliminated. However, in present embodiment 3, the semiconductor chip CP1 is mounted on the thick portion D1a of the die pad DP1 and the thin portion D1b via the bonding material BD1, and the semiconductor chip CP2 is mounted on the thick portion D2a and the thin portion DP2 of the die pad via the bonding material BD2. Therefore, in the present embodiment 3, not only the thick portion D1a, D2a of the die pad DP1, DP2 but also the thin portion D1b, DP2b of the die pad DP1, DP2 contributes to the mounting area of the semiconductor chip CP1, CP2, so that the thin portion D1b, DP2b cannot be eliminated. That is, in the present embodiment 3, since it is intended to increase the creepage distance (distance L4) between the exposed portions of the die pad DP1, DP2 on the main surface MRb of the sealing portion MR, in the die pad DP1, DP2, the thin portion D1b, DP2b is provided at a position overlapping the semiconductor chip CP1, CP2 in plan view.
Further, it is assumed that, unlike present embodiment 3, the semiconductor chip CP1 is mounted only on the thin portion D1b of the die pad DP1, the semiconductor chip CP1 does not have a portion that overlaps the thick portion D1a in a plan view, and the semiconductor chip CP2 is mounted only on the thin portion D2b of the die pad DP2, and the semiconductor chip CP2 does not have a portion that overlaps the thick portion D2a in a plan view. In this case, since the thick portion D1a, D2a of the die pad DP1, DP2 does not exist directly under the semiconductor chip CP1, CP2, the heat generated in the semiconductor chip CP1, CP2 is less likely to be conducted to the thick portion D1a, D2a of the die pad DP1, DP2, and is less likely to be emitted to the outside of the semiconductor device PKG3 from the thick portion D1a, D2a of the die pad DP1, DP2.
On the other hand, present 3, in embodiment the semiconductor chip CP1 die pad DP1 is mounted on the thick portion D1a and the thin portion D1b, the semiconductor chip CP1 has a portion that overlaps the thick portion D1a in a plan view, and the semiconductor chip CP2 is mounted on the thick portion D2a and the thin portion D2b of the die pad DP2, and the semiconductor chip CP2 has a portion that overlaps the thick portion D2a in a plan view. Therefore, since the thick portion D1a, D2a of the die pad DP1, DP2 exists directly under the semiconductor chip CP1, CP2, the heat generated in the semiconductor chip CP1, CP2 is easily conducted to the thick portion D1a, D2a of the die pad DP1, DP2, and is easily discharged to the outside of the semiconductor device PKG3 from the thick portion D1a, D2a of the die pad DP1, DP2.
Therefore, in present embodiment, the boundary between the thick portion D1a and the thin portion D1b in the die pad DP1 is disposed at a position overlapping with the semiconductor chip CP1 in plan view, and the boundary between the thick portion D2a and the thin portion D2b in the die pad DP2 is disposed at a position overlapping with the semiconductor chip CP2 in plan view.
Also in present embodiment 3, the height position of the die pad DP1 and the height position of the die pad DP2 are the same in the thickness direction (Z direction) of the sealing portion MR. Therefore, it is easy to perform the wire bonding step at the time of manufacturing the semiconductor device PKG3. Therefore, it is easy to control the process of the wire bonding step at the time of manufacturing. In addition, the manufacturing yield of the semiconductor device PKG3 can be improved, and the manufacturing cost of the semiconductor device PKG3 can be suppressed.
The construction of a semiconductor device PKG4 of the present embodiment 4 will be described by referring to
Note that
The semiconductor device PKG4 according to the embodiment 4 will be described below with a focus on the difference between the semiconductor device PKG1 of the embodiment 1 and the semiconductor device PKG4 of the embodiment 4.
In the semiconductor device PKG4 of the present embodiment 4, the groove TR is not formed on the main surface MRb of the sealing portion MR, and a protruding portion TB is formed instead of the groove TR. In the main surface MRb of the sealing portion MR, the formation position of the protruding portion TB is basically the same as the formation position of the trench TR. That is, in the main surface MR of the sealing portion MRb, between the exposed portion of the die pad DP1 (back surface DP1b) and the exposed portion of the die pad DP2 (back surface DP2b), the protruding portion TB of the sealing portion is formed. Specifically, in the main surface MRb of the sealing portion MR, the protruding portion TB is formed (extends) along the X-direction so as to cross the region between the exposed portion (back surface DP1b) of the die pad DP1 and the exposed portion (back surface DP2b) of the die pad DP2. The main surface MRb of the sealing portion MR is a substantially flat surface except for the protruding portion TB, but protrudes locally in the protruding portion TB. The protruding portion TB is constituted by a top surface (upper surface) and both side walls (both side surfaces), and the top surface and both side walls are substantially parallel to the X-direction.
In addition, in the above embodiment 1, the outer lead portions of the respective lead LD1, LD2 are bent toward the main surface MRb of the sealing portion, but in the present embodiment 4, the outer lead portions of the respective lead LD1, LD2 are bent toward the main surface MRa of the sealing portion. Specifically, the outer lead portions of the respective lead LD1, LD2 are bent so that the lower surface near the end portion of the outer lead portion is located on substantially the same plane as the main surface MRa of the sealing portion MR.
Therefore, in the present embodiment 4, the sealing portion MR has a main surface MRb of upper surface, and the sealing portion MR has a main surface MRa of a lower surface. When the semiconductor device PKG4 is mounted on a mounting substrate or the like, the semiconductor device PKG4 is mounted on the mounting substrate so that the main surface MRa of the sealing part MR serves as the mounting surface and the main surface MRa of the sealing part MR faces the mounting substrate PB.
Other configurations of the semiconductor device PKG4 of the present embodiment 4 are substantially the same as those of the semiconductor device PKG1 of present embodiment 1, and therefore, repeated explanation thereof will be omitted here.
The manufacturing step of the semiconductor device PKG4 of the present embodiment 4 is different from that of the present embodiment 1 in the following points.
That is, by performing the molding step, to form a sealing portion MR, a portion corresponding to the protrusion TB is provided in the mold for forming the sealing portion MR so that the sealing portion MR has a protrusion TB at the stage where the sealing portion is formed. Alternatively, it is also possible to form the protrusion TB on the sealing portion MR by forming the sealing portion MR having no protrusion TB in the molding step and then grinding or polishing the portion other than the portion serving as the protrusion TB in the main surface MRb of the sealing portion MR until the back surface DP1b, DP2b of the die pad DP1, DP2 is exposed. The former (contrivance of the mold) can simplify the manufacturing step.
In addition, in the present embodiment 4, the bending direction in bending the lead LD1, LD2 is opposite to the bending direction in the embodiment 1.
As shown in
In
Also in the present embodiment 4, since the sealing portion MR is exposed from the main surface MRb of the sealing portion DP1, DP2 to the back surface DP1b, DP2b of the die pad DP1, DP2, heat generated in CP1, CP2 of the semiconductor chip is easily discharged from the die pad DP1, DP2 to the outside of the semiconductor device PKG1.
Further, in the present embodiment, in the main surface MRb of the sealing portion MR, it is possible to suppress or prevent the occurrence of a discharge between the back surface DP1 of the die pad DP1 exposed from the main surface MRb of the sealing portion MR and the back surface DP2 of the die pad DP1b by forming the protruding portion TB of the sealing portion MR between the back surface DP2 of the die pad DP1b and the back surface DP2b of the die pad DP2b. The reason for this will be described below.
That is, in the present embodiment 4, in the main surface MR of the sealing portion MRb, the exposed portion of the die pad MRb (back surface DP1, DP2) in the main surface DP1, DP2 of the sealing portion DP1b, DP2b (corresponding to the examined example 1 in
That is, when the convex portion TB is formed, when the discharge occurs between the exposed portion (back surface DP1b, DP2b) of the die pad DP1, DP2 in the main surface MRb of the sealing portion MR, since the discharge path will include both side walls and the top surface of the convex portion TB, as compared with the case where the convex portion TB is not formed, the discharge path becomes longer, result, the exposed portion of the die pad DP1, DP2 (back surface DP1b, DP2b) discharge is less likely to occur between. Therefore, as in the present embodiment, it is possible to suppress or prevent a discharge between exposed portions (back surface MR) of the die pad DP1, DP2 in the main surface MRb of the sealing portion DP1b, DP2b, by forming the exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2 between the exposed portions (back surface TB) of the sealing portion MR, the main surface MRb of the sealing portion MR.
Further, in the present embodiment 4, since the convex portion TB is provided on the main surface MRb of the sealing portion MR, it is possible to increase the creepage distance between the exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2 on the main surface MRb of the sealing portion MR without increasing the distance between the die pad DP1, DP2. Therefore, the planar dimension (planar area) of the semiconductor device PKG4 can be suppressed. In addition, it is possible to prevent or prevent the wire BW3 from contacting each other when the sealing portion MR is formed.
Further, in the main surface MRb of the sealing portion MR, the convex portion TB is formed so as to cross a region between the back surface DP1b of the die pad DP1 and the back surface DP2b of the die pad DP2 (refer to
Further, in the main surface MRb of the sealing portion MR, since it is possible to suppress or prevent a discharge between exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2 on the main surface DP1 of the sealing portion MR as long as the convex portion TB crosses the region between the back surface DP1b of the die pad MR and the back surface DP2b of the die pad DP2, there may be cases where the convex portion TB has not reached the side surface of the sealing portion. However, it is more preferable that the convex portion TB reaches both side surfaces (both side surfaces located on opposite sides) of the sealing portion MR, so that the convex portion TB on the sealing portion MR can be easily formed, and the discharge-suppressing effect can also be enhanced.
Further, as the height H1 of the convex portion TB is increased, the creepage distance between the exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2 in the main surface MRb of the sealing portion MR is increased, so that a discharge is less likely to occur between the exposed portions (back surface DP1b, DP2b) of the die pad DP1, DP2. Therefore, it is preferable that the height TB of the sealing portion MR on the convex portion H1 is increased to some extent (increased), and in this viewpoint, it is preferable that the height H1 of the convex portion TB is larger than the respective thicknesses of the die pad DP1, DP2.
Also in the present embodiment 4, the height position of the die pad DP1 and the height position of the die pad DP2 are the same in the thickness direction (Z direction) of the sealing portion MR. Therefore, it is easy to perform the wire bonding step at the time of manufacturing the semiconductor device PKG4.
The construction of a semiconductor device PKG5 of the present embodiment 5 will be described by referring to
The semiconductor device PKG5 according to the embodiment 5 will be described below with a focus on the difference between the semiconductor device PKG1 of the embodiment 1 and the semiconductor device PKG5 of the embodiment 5.
In the semiconductor device PKG5 of the present embodiment 5, the groove TR is not formed on the main surface MRb of the sealing portion MR, and the convex portion TB is not formed. Therefore, in present embodiment 5, the main surface MRb of the sealing portion MR is a flat surface (more specifically, a flat surface substantially parallel to the X direction and the Y direction). Similarly to the embodiment 1, in present embodiment 2, the main surface MRa of the sealing portion MR is a flat surface (more specifically, a flat surface substantially parallel to the X direction and the Y direction).
In addition, in the above embodiment 1, the outer lead portions of the respective lead LD1, LD2 are bent toward the main surface MRb of the sealing portion, but in the present embodiment 5, the outer lead portions of the respective lead LD1, LD2 are bent toward the main surface MRa of the sealing portion. Specifically, the outer lead portions of the respective lead LD1, LD2 are bent so that the lower surface near the end portion of the outer lead portion is located on substantially the same plane as the main surface MRa of the sealing portion MR.
Therefore, in the present embodiment 5, the sealing portion MR has a main surface MRb of upper surface, and the sealing portion MR has a main surface MRa of a lower surface. When the semiconductor device PKG5 is mounted on a mounting substrate or the like, the semiconductor device PKG5 is mounted on the mounting substrate so that the main surface MRa of the sealing part MR serves as the mounting surface and the main surface MRa of the sealing part MR faces the mounting substrate PB.
Other configurations of the semiconductor device PKG5 of the present embodiment 5 are substantially the same as those of the semiconductor device PKG1 of the present embodiment 1, and therefore, repeated explanation thereof will be omitted here.
The manufacturing step of the semiconductor device PKG5 of the present embodiment 5 is different from that of the present embodiment 1 in the following points.
That is, in the present embodiment 5, in the sealing portion MR forming step, the groove portion TR may not be formed on the sealing portion MR. In this respect, the manufacturing step can be simplified. However, in the present embodiment 5, after the semiconductor device PKG5 is mounted on the mounting substrate PB5, a resin portion PT forming step to be described later is required.
In addition, in the present embodiment 5, the bending direction in bending the lead LD1, LD2 is opposite to the bending direction in the embodiment 1.
As shown in
Then, the heat-sink HS is disposed and bonded to the exposed portion (back surface DP2b) of the die pad DP2 from the main surface MRb of the sealing portion MR via the bonding material BD3. As a result, the heat generated in the semiconductor chip CP2 is conducted to the heat sink HS via the bonding material BD2, the die pad DP2, and the bonding material BD3, and can be radiated from the heat sink HS into the outside air. As the bonding material BD, it is preferable to use a bonding material having a higher thermal conductivity. In some cases, the heat sink HS is not disposed, heat generated in the semiconductor chip CP2 is conducted to the die pad DP2 through the bonding material BD2, and is dissipated to the outside air from the back surface DP2b of the die pad DP2.
In the present embodiment 5, after the semiconductor device PKG5 is mounted on the mounting substrate PB5, a resin portion (potting resin, sealing resin) PT is formed so as to cover the exposed portion (back surface DP1b) of the die pad DP1 from the main surface MRb of the sealing portion MR. When the heat sink HS is disposed on the back surface DP2b of the die pad DP2, it is preferable to form the resin portion PT after the heat sink HS is disposed.
The resin portion PT is made of, for example, a resin material such as a thermosetting resin material, and may include fillers and the like. For example, the resin portion PT can be formed using an epoxy-resin or the like containing fillers. The resin-part PT can be formed by a potting method or the like. For example, the resin portion PT can be formed by applying or dropping a resin material for resin portion PT so as to cover the back surface DP1b of the die pad DP1 exposed from the main surface MRb of the sealing portion MR, and then curing the resin material.
In the embodiment 5 of the semiconductor device PKG5, from the main surface MR of the sealing portion MRb, the back surface DP1, DP2 of the die pad DP1b, DP2b is exposed, but the resin portion PT is formed so as to cover the back surface DP1b of the die pad DP1 exposed from the main surface MR of the sealing portion after the semiconductor device PKG5 is mounted on the mounting substrate PB5. Therefore, in the step of operating the semiconductor device PKG5, the back surface DP1b of the die pad DP1 exposed from the main surface MRb of the sealing portion MR is covered with the resin portion PT and is not exposed. Therefore, even if a high-potential difference occurs between the die pad DP1 on which the semiconductor chip CP1 is mounted and the die pad CP2 on which the semiconductor chip DP2 is mounted, a discharge (corona discharge, creepage discharge) does not occur between the die pad DP1 and the die pad DP2.
Further, the sealing portion PT covers the back surface DP1b of the die pad DP1 exposed from the main surface MRb of the sealing portion MR, but does not cover the back surface DP2b of the die pad DP2 exposed from the main surface MRb of the sealing portion MR. Heat generated by the semiconductor chip CP2 can be emitted from the die pad DP2 to the outside of the semiconductor device PKG5 because the back surface DP2b of the die pad DP2 on which the semiconductor chip CP2 having a larger heat generation value than that of the semiconductor chip CP1 is mounted is not covered with the sealing portion PT.
Also in the present embodiment 5, the height position of the die pad DP1 and the height position of the die pad DP2 are the same in the thickness direction (Z direction) of the sealing portion MR. Therefore, it is easy to perform the wire bonding step at the time of manufacturing the semiconductor device PKG5.
When the semiconductor devices PKG˜PKG5 of the embodiments 1˜5 are compared to one another, the semiconductor devices PKG1, PKG3, PKG5 of the embodiments 1, 3, 5 have a better transportability than the semiconductor devices PKG2, PKG4 of the embodiments 2, 4. The reason for this is that the semiconductor device PKG2 according to the embodiment 2 has a step MR on the main surface of the sealing portion DS, and the semiconductor device PKG4 according to the embodiment 4 has a convex portion TB on the main surface of the sealing portion MR, thus there is a possibility that the transportability of the semiconductor device is to be lowered by the step DS and the convex portion, while there is no fear that the transportability of the semiconductor devices PKG1, PKG3, PKG5 according to the embodiments 1, 3, 5 is to be lowered.
The invention made by the present inventor has been described above in detail based on the embodiment, but the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without departing from the gist thereof.
