1. Field of the Invention
The present invention relates to a connecting technique for a semiconductor device in which a plurality of semiconductor chips, such as power semiconductor devices, are provided on a substrate.
2. Description of the Background Art
In such a semiconductor device, a metal heat spread is provided over a metal base plate with an insulating layer therebetween, and semiconductor chips such as IGBTs and diodes are bonded on the heat spread with solder. Methods for connecting such a plurality of semiconductor chips include wire bonding in which connections are made with wires like aluminum wires (see Japanese Patent Application Laid-Open No. 11-086546 (1999)) and direct lead bonding in which a lead frame is directly connected to the semiconductor chips (DLB; see Japanese Patent Application Laid-Open No. 2007-142138).
For wire bonding, the number of wires increases when an increased number of chips are provided on the substrate, and then the productivity is lowered.
For DLB, the resistance and inductance components are reduced as compared with wire bonding, and it has the advantage of high heat cycle property. However, when connections are made with a plurality of chips, the solder thicknesses in bonded portions vary and then the heat cycle property is lowered. Also, complicated bending processing is necessary in order to adapt to a plurality of chips. This increases the number of molding process steps with molds and increases manufacturing costs.
At present, semiconductor devices using materials capable of high-temperature operations, typically SiC, are under development, and structures stably connecting a plurality of chips at high temperatures are demanded.
An object of the present invention is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property.
A semiconductor device according to the present invention includes a plurality of semiconductor chips and a plate electrode. The plurality of semiconductor chips are formed on a substrate. The plate electrode is full-cut into a given pattern for connecting electrodes of the plurality of semiconductor chips, and has half-cut portions formed by half-pressing. Raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips.
The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of semiconductor chips. Accordingly, complicated bending processing is not necessary in order to make a complicated configuration adapted to semiconductor chips, and so it can be made at low cost with a less number of molds. Also, the number of process steps does not increase even when the number of chips is increased, and so it can be made at low cost from the aspect of reducing the number of process steps.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
(Preliminary Techniques)
In
In the DLB shown in
Accordingly, the present invention provides a low-cost plate electrode connecting a plurality of semiconductor chips 5 by forming a pattern by full-cutting and half-pressing a single plate.
<Structure>
Also, at corners of the guard ring 6 having a smaller curvature, the electric field is higher than at straight portions. Accordingly, as shown in
As shown in
Also, the emitter electrodes connected to the electrode posts 9 are connected to a laminate bus bar together with an emitter electrode of another semiconductor device forming a control system. Laminate bus bars have heat-resistant temperature restrictions, and usually temperatures of 105° C. or less are recommended. Accordingly, as shown in
For semiconductor chips 5 such as IGBTs and diodes, wide band gap semiconductors such as SiC having wider band gap than Si may be used. Wide band gap semiconductors include GaN material and diamond as well as SiC. The plate electrode 1 of the present invention has high heat cycle property, so that it can be stably used in semiconductor devices provided with high-temperature-operable semiconductor chips 5 mentioned above.
<Producing Process>
First, a single plate to be the plate electrode 1 shown in
Next, the plate electrode 1 is half-pressed to form half-cut portions 1a in parts of the plate electrode 1 (
Furthermore, embossing processing is applied to the half-cut portions 1a, to form dot-like embossed portions 1b (
As described so far, the plate electrode 1 of the present invention does not require complicated bending processing to adapt to a plurality of semiconductor chips, so that it can be formed with a less number of molds and at low cost. Also, unlike wire bonding, the number of process steps does not increase even when the number of chips increases, so that it is at low cost also from the aspect of reducing the number of process steps. Thus, the semiconductor device provided with the plate electrode 1 of the present invention can be manufactured at low cost.
<Effects>
A semiconductor device of the present invention includes a plurality of semiconductor chips 5 formed on a substrate and a plate electrode 1 that is full-cut into a given pattern connecting electrodes of the plurality of semiconductor chips 5, and the plate electrode 1 has half-pressed, half-cut portions 1a, and the raised sides of the half-cut portions 1a are bonded with the electrodes of the semiconductor chips 5, whereby a semiconductor device having a connecting structure adapted to a plurality of semiconductor chips can be manufactured at low cost.
Also, in the semiconductor device of the present invention, the plate electrode 1 further has embossed portions 1b that are formed by embossing processing in the half-cut portions 1a to project from the raised sides of the half-cut portions 1a. The embossed portions 1b abut on the semiconductor chips 5 and the thickness of the bonding material 8 is ensured for the height of the embossed portions 1b. Accordingly, when a plurality of semiconductor chips 5 are connected through the plate electrode 1, the thickness of the bonding material 8 can be uniform in bonded portions, and the heat cycle property is improved.
Also, in the semiconductor device of the present invention, a semiconductor chip 5 has a guard ring 6 around its periphery, and the interval between the portion out of the half-cut portion 1a of the plate electrode 1 and the guard ring 6 of the semiconductor chip 5 is not less than 0.6 mm, whereby the electric field at the surface of the guard ring 6 is suppressed and leakage current is suppressed.
Also, in the semiconductor device of the present invention, regions of the plate electrode 1 corresponding to corners of the guard ring 6 of the semiconductor chip 5 are removed, whereby the electric fields at the corners where the electric fields most concentrate are alleviated and leakage current is suppressed.
Also, in the semiconductor device of the present invention, the height of the raised portions of the half-cut portions 1a is not more than a half of the thickness of the plate electrode 1, whereby the formation is facilitated with high dimensional accuracy, allowing the plate electrode 1 to be easily formed in a large area.
Also, the semiconductor device of the present invention includes an electrode post 9 provided on the plate electrode 1 in a region where no semiconductor chip 5 exists underneath, and an external electrode connected to the electrode post 9. Accordingly, in the transfer mold process, the upper surface of the electrode post 9 is kept parallel also to the external electrode due to the bend effect of the plate electrode 1, whereby the solder thickness at the bonded surface between the electrode post 9 and the external electrode is uniform and heat cycle property is ensured. Also, when ultrasonic (US) bonding is used, a uniform pressure can be applied to the bonded surface.
Also, in the semiconductor device of the present invention, at least part of the plate electrode 1 located around the electrode post 9 is removed, whereby the heat resistance from the semiconductor chips 5 to the electrode post 9 is large, and the temperature of the external electrode connected to the electrode post 9 can be within a proper range.
Also, in the semiconductor device of the present invention, when high-temperature operating semiconductor chips 5 are provided by forming the semiconductor chips 5 with a wide band gap semiconductor, the heat cycle property of the plate electrode 1 is not lowered and the insulating performance of the semiconductor chips 5 can be enhanced.
While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.
Number | Date | Country | Kind |
---|---|---|---|
2010-218256 | Sep 2010 | JP | national |
Number | Name | Date | Kind |
---|---|---|---|
6078514 | Takemae et al. | Jun 2000 | A |
7589400 | Hozoji et al. | Sep 2009 | B2 |
20040012064 | Yoshizaki et al. | Jan 2004 | A1 |
20040188706 | Chang et al. | Sep 2004 | A1 |
20060268524 | Uehara et al. | Nov 2006 | A1 |
20070114577 | Narazaki | May 2007 | A1 |
20080012045 | Muto et al. | Jan 2008 | A1 |
20100078803 | Andou et al. | Apr 2010 | A1 |
20100089607 | Nakamura et al. | Apr 2010 | A1 |
Number | Date | Country |
---|---|---|
1758522 | Apr 2006 | CN |
101 56 626 | Jun 2003 | DE |
10 2006 051 454 | Sep 2007 | DE |
10 2007 039 916 | Feb 2009 | DE |
11-86546 | Mar 1999 | JP |
2000-277557 | Oct 2000 | JP |
2001-156219 | Jun 2001 | JP |
2002-217364 | Aug 2002 | JP |
2007-142138 | Jun 2007 | JP |
2008-21796 | Jan 2008 | JP |
Entry |
---|
German Office Action issued Jan. 17, 2013 in Patent Application No. 10 2011 082 781.1 with English Translation. |
Japanese Office Action issued Jul. 30, 2013, in Japan Patent Application No. 2010-218256 (with Partial English translation). |
Chinese Office Action issued Nov. 27, 2013 in Chinese Application No. 2011/10198380.0 with English Translation. |
Number | Date | Country | |
---|---|---|---|
20120074516 A1 | Mar 2012 | US |