The present invention relates to packaging of microelectronic devices, especially the packaging of semiconductor devices.
Microelectronic devices generally comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide, commonly called a die or a semiconductor chip. Semiconductor chips are commonly provided as individual, prepackaged units. In some unit designs, the semiconductor chip is mounted to a substrate or chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board.
The active circuitry is fabricated in a first face of the semiconductor chip (e.g., a front surface). To facilitate electrical connection to the active circuitry, the chip is provided with bond pads on the same face. The bond pads are typically placed in a regular array either around the edges of the die or, for many memory devices, in the die center. The bond pads are generally made of a conductive metal, such as copper, or aluminum, around 0.5 micron (μm) thick. The bond pads could include a single layer or multiple layers of metal. The size of the bond pads will vary with the device type but will typically measure tens to hundreds of microns on a side.
Through-silicon vias (TSVs) can be used to provide electrical connections between the front surface of a semiconductor chip on which bond pads are disposed, and a rear surface of a semiconductor chip opposite the front surface. Conventional TSV holes may reduce the portion of the first face that can be used to contain the active circuitry. Such a reduction in the available space on the first face that can be used for active circuitry may increase the amount of silicon required to produce each semiconductor chip, thereby potentially increasing the cost of each chip.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/O's.” These I/O's must be interconnected with the I/O's of other chips. The interconnections should be short and should have low impedance to minimize signal propagation delays. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines. For example, structures which provide numerous short, low-impedance interconnects between complex chips can increase the bandwidth of the search engine and reduce its power consumption.
Despite the advances that have been made in semiconductor via formation and interconnection, further improvements can be made to enhance the processes for making connections between front and rear chip surfaces, and to the structures which can result from such processes.
In a particular embodiment, the dielectric layer 105 can include one or more layers of dielectric material having a low dielectric constant, i.e., a “low-k” dielectric layer, between and around the metal wiring patterns which provide electrical interconnection for the microelectronic element. Low-k dielectric materials include porous silicon dioxide, carbon-doped silicon dioxide, polymeric dielectrics, and porous polymeric dielectrics, among others. In a porous low-k dielectric layer, the dielectric layer can have substantial porosity, which reduces the dielectric constant of the dielectric material relative to a nonporous layer of the same material. Dielectric materials typically have a dielectric constant significantly above 1.0, but air which occupies open spaces within a porous dielectric material has a dielectric constant of about 1.0. In this way, some dielectric materials can achieve reductions in the dielectric constant by having substantial porosity.
However, some low-k dielectric materials, such as polymeric dielectric materials and porous dielectric materials, withstand much less mechanical stress than traditional dielectric materials. Particular types of operating environments and ways that the microelectronic element may be tested can present stress at or near a limit that the low-k dielectric material can tolerate. The microelectronic assemblies described herein provide improved protection for the low-k dielectric layer of a microelectronic element by moving the locations where stress is applied to the microelectronic element away from the low-k dielectric layer 105. In this way, manufacturing, operation and testing can apply much reduced stresses to the low-k dielectric layer, thus protecting the low-k dielectric layer. As further seen in
A plurality of conductive elements 114 extend within the first and second openings and are electrically coupled to the conductive pads 106. The conductive elements 114 are exposed at an exposed outwardly-facing surface 118 of the first element. In one example, the conductive elements 114 can include metal features which are formed by depositing a metal in contact with exposed surfaces of the conductive pads 106. Various metal deposition steps can be used to form the conductive elements, as described in further detail below. The first element can include one or more passive circuit elements, e.g., capacitors, resistors or inductors, or a combination thereof, which while not specifically shown in
As further provided by the package 100, the first element can function as a carrier which mechanically supports the chip. The thickness 112 of the chip typically is less than or equal to the thickness 116 of the first element. When the first element and the chip are CTE-matched and the first element is bonded to the front face of the chip, the chip can be relatively thin in comparison to the first element. For example, when the first element has a CTE that matches the chip, the thickness 112 of the chip may be only a few microns, because stresses applied to the conductive elements 114 are spread over the dimensions and thickness 116 of the first element, rather than being applied directly to the conductive pads 106. For example, in a particular embodiment, the thickness 120 of the semiconductor region 107 of the chip may be less than one micron to a few microns. The chip, the first element bonded thereto, and the conductive elements 114 together provided a microelectronic assembly 122 which can be mounted and further interconnected in a microelectronic package.
As further seen in
As will be further understood, the second conductive elements 154B are exposed at a surface of the wafer 200 and can be available for forming electrically conductive interconnections between the microelectronic assembly (
Referring to
After bonding the packaging layer 110 to the wafer 200, a thickness of the packaging layer 110 can be reduced from an original thickness to a reduced thickness 116, as shown in
Hereinafter, a series of fragmentary sectional views are used to illustrate stages in a method of fabricating a microelectronic assembly according to an embodiment of the invention. The steps shown therein may typically be performed at wafer-level, i.e., prior to severing a semiconductor wafer (
The process of forming the first and second openings can be as generally described in any or all of United States Patent Publication No. 20080246136A1, or United States applications, each filed Jul. 23, 2010: application Ser. Nos. 12/842,717, 12/842,612, 12/842,669; 12/842,692; 12/842,587, the disclosures of which are incorporated herein by reference, with the exception that the first and second openings extend through a packaging layer and a bonding layer rather than through the chip, and the second opening exposes a portion of an outwardly-facing upper surface of a conductive pad rather than the lower pad surface.
As further seen in
Electrophoretic deposition forms a continuous and uniformly thick conformal coating on conductive and/or semiconductive exterior surfaces of the assembly. In addition, the electrophoretic coating can be deposited so that it does not form on the surface 108A of the dielectric bonding layer 108 overlying the upper surface 172 of the conductive pad 106, due to its dielectric (nonconductive) property. Stated another way, a property of electrophoretic deposition is that is does not form on a layer of dielectric material overlying a conductor provided that the layer of dielectric material has sufficient thickness, given its dielectric properties. Typically, electrophoretic deposition will not occur on dielectric layers having thicknesses greater than about 10 microns to a few tens of microns. The conformal dielectric layer 138 can be formed from a cathodic epoxy deposition precursor. Alternatively, a polyurethane or acrylic deposition precursor could be used. A variety of electrophoretic coating precursor compositions and sources of supply are listed in Table 1 below.
In another example, the dielectric layer can be formed electrolytically. This process is similar to electrophoretic deposition, except that the thickness of the deposited layer is not limited by proximity to the conductive or semiconductive surface from which it is formed. In this way, an electrolytically deposited dielectric layer can be formed to a thickness that is selected based on requirements, and processing time is a factor in the thickness achieved.
The dielectric layer 138 formed in this manner can conform to contours of the interior surfaces 121, 123 of the first and second openings.
After forming the dielectric layer 138, a conductive layer 114A (
Thereafter, as seen in
As further shown in
Alternatively, without detaching the carrier from the packaging layer 110, steps can be performed to fabricate a microelectronic assembly which further includes a second conductive element 154 as seen in
Next, as seen in
Thereafter, the carrier and bonding layer 182 can be detached, resulting in a microelectronic assembly as seen in
In a variation of the above-described embodiment, instead of forming a conformal conductive layer 154A on dielectric layer 158 and then forming an additional dielectric layer 160 overlying the conductive layer within the opening in the wafer 200 as seen in
Moreover, as in the above-described embodiments (
A process capable of forming the microelectronic assembly (
Thereafter, as illustrated in
Subsequently, as illustrated in
Next, as illustrated in
As seen in
Referring now to
Subsequently, as shown in
In another variation, when thinning the packaging layer 410 as seen in
Microelectronic assemblies according to other variations of the above-described embodiment (
A dielectric region 928 is provided within the openings 911, 913 which typically contacts upper surfaces 907 of the conductive pads 906, wherein the first conductive elements extend through the dielectric region. A portion 928A of the dielectric region can overlie an outwardly-facing surface 926 of the packaging layer. Electrically conductive pads 916 exposed at a surface of the dielectric region 928 may be provided as portions of the conductive element 914, and can be disposed atop the dielectric region 928. Alternatively, the electrically conductive pads 916 can be omitted.
The microelectronic assembly 990 can be fabricated by processing similar to that described above with reference to
As further seen in
Turning now to
Then, in like manner as described above (
A dielectric layer 1419 may then be formed atop the surface 1417, as seen in
The structure and fabrication of the microelectronic assemblies and incorporation thereof into higher-level assemblies can include structure, and fabrication steps which are described in one or more of the following commonly owned co-pending United States applications each filed on Dec. 2, 2010: U.S. Provisional Application No. 61/419,037; and U.S. Nonprovisional application Ser. No. 12/958,866; and the following U.S. applications each filed Jul. 23, 2010: application Ser. Nos. 12/842,717; 12/842,651; 12/842,612; 12/842,669; 12/842,692; and 12/842,587; the disclosures of all such applications being incorporated by reference herein. The structures discussed above provide extraordinary three-dimensional interconnection capabilities. These capabilities can be used with chips of any type. Merely by way of example, the following combinations of chips can be included in structures as discussed above: (i) a processor and memory used with the processor; (ii) plural memory chips of the same type; (iii) plural memory chips of diverse types, such as DRAM and SRAM; (iv) an image sensor and an image processor used to process the image from the sensor; (v) an application-specific integrated circuit (“ASIC”) and memory. The structures discussed above can be utilized in construction of diverse electronic systems. For example, a system 1500 in accordance with a further embodiment of the invention includes a structure 1506 as described above in conjunction with other electronic components 1508 and 1510. In the example depicted, component 1508 is a semiconductor chip whereas component 1510 is a display screen, but any other components can be used. Of course, although only two additional components are depicted in
As these and other variations and combinations of the features discussed above can be utilized without departing from the present invention, the foregoing description of the preferred embodiments should be taken by way of illustration rather than by way of limitation of the invention.
While the above description makes reference to illustrative embodiments for particular applications, it should be understood that the claimed invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope of the appended claims.
The present application is a divisional of U.S. patent application Ser. No. 13/051,424, filed Mar. 18, 2011, which claims the benefit of the filing date of U.S. Provisional Patent Application No. 61/419,033, filed Dec. 2, 2010, the disclosures of which are hereby incorporated herein by reference.
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Number | Date | Country | |
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20140206147 A1 | Jul 2014 | US |
Number | Date | Country | |
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61419033 | Dec 2010 | US |
Number | Date | Country | |
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Parent | 13051424 | Mar 2011 | US |
Child | 14224379 | US |