1. Field of the Invention
The invention relates in general to a substrate and a package and methods of manufacturing the same, and more particularly to the substrate having an embedded single patterned metal layer, and a package applying the substrate, and methods of manufacturing the substrate and the package.
2. Description of the Related Art
The integrated circuit (IC) package technology plays an important role in the electronics industry. Electronic packaging is for protecting and supporting circuit configuration, creating a path for heat dissipation and providing modularized standard specification form factors for the parts. Electronic packaging in 1990's mainly employs ball grid array (BGA) packaging which is excellent in heat dissipation, has excellent electrical properties and is capable of increasing leads and effectively reducing the surface area of the package.
As lightweight, thinness, compactness, and high efficiency have become universal requirements of consumer electronic and communication products, the chip requires superior electrical properties, a smaller overall volume, and a larger number of I/O ports. As the number of I/O ports increases, the pitch of the integrated circuit is reduced. Thus, it is very difficult to achieve a high efficiency wiring on a BGA substrate or a lead frame substrate. For example, the density of I/O ports increases dramatically starting with the 0.18 μm IC node or high speed (such as 800 MHz above) IC design. Flip chip technology, having high I/O density and excellent electrical properties, is a solution to the above problem and has become one of the mainstreams in the development of electronic carriers. It is a main goal for the manufacturers to develop a substrate with higher density of I/O ports, smaller trace pitches and excellent electrical properties. Besides, in addition to the request of the flip chip technology, the request of systematic integration of the downstream products is also getting more and more urgent. Thus, the multi-chip module (MCM) process has an increased need of the MCM carrier. The MCM carrier and the flip chip carrier have great market potential.
Along with the maturity in the chip scale packaging (CSP) technology, system in package SiP, the systematic semiconductor integration on a package level, which function-wise and cost-wise, has become a mainstream in packaging technology. As the product size becomes smaller and smaller and the function becomes more and more versatile, the SiP technology is used to satisfy the market demands. SiP technology integrates chips of different functions, passive components and other modules together, so that the electronic products have versatile functions. SiP technology also includes different technologies such as 2-dimensional multi-chip module packages and 3-dimensional stacked packages which stack chips of different functions for saving space. As for what type of packaging is most suitable for an application is determined according to the needs of the application. The SiP technology has a wide range of definition, and employs many types of bonding technologies such as wire bonding, flip chip bonding and hybrid-type bonding.
Take the SiP package for example. The SiP package integrates the dice of different digital or analogue functions and bonds the dice on a chip carrier by way of bump bonding or wire bonding. The carrier having embedded passive components or traces possesses electrical properties and is called the integrated substrate or the functional substrate.
For another type of integrated substrate, the through hole in the substrate could be filled with the conductive material such as copper by plating procedure, and the copper layers on two sides of the core are then patterned to form the metal trace.
Since the substrate depicted in
To satisfy the requirements of small-sized electronic products, it is a trend to develop a substrate structure with high density of I/O ports and small trace pitches without sacrificing the electrical properties. However, it is difficult to further reduce the size of the conventional structures (such as substrates of
The present invention provides structures of the substrate having a single patterned metal layer, and the package with this substrate, and methods of manufacturing the same. The substrate of the disclosure merely includes a patterned metal layer (as conductive traces) and two dielectric layers, which reduces the thickness of the substrate. This extra thin substrate is particularly suitable for the application of small-sized, low profile products. Also, the simplified process for manufacturing the substrate is suitable for mass production, while high production yield is still maintained. Compared to the prior art, the substrate structure of the disclosure satisfies the desired requirements of the electronic product with thin profile and low cost.
According to the first aspect of the invention, a substrate having a single patterned metal layer is provided, including a first patterned dielectric layer having a top surface and a bottom surface, a patterned metal layer embedded in the first patterned dielectric layer, and a second patterned dielectric layer formed above the patterned metal layer and the first patterned dielectric layer. A top surface of the patterned metal layer is coplanar with the top surface of the first patterned dielectric layer, wherein at least part of the patterned metal layer are exposed from a pattern of the first patterned dielectric layer so as to form plural first contact pads for downward electrical connection externally. The second patterned dielectric layer at least exposes parts of the patterned metal layer to form plural second contact pads at the top surface of the patterned metal layer for upward electrical connection externally.
According to the second aspect of the invention, a package with the substrate having a single patterned metal layer is provided, comprising the substrate described in the first aspect, at least a die electrically connected to the second contact pads of the substrate, and a molding compound disposed on the top surface of the first patterned dielectric layer so as to cover the first patterned dielectric layer, the patterned metal layer, the second patterned dielectric layer and the die.
According to the third aspect of the invention, a method of manufacturing a substrate having single patterned metal layer is disclosed. First, a patterned metal layer is formed. A first patterned dielectric is then formed on a bottom surface of the patterned metal layer, and a top surface of the first patterned dielectric layer is coplanar with a top surface of the patterned metal layer. At least parts of the bottom surface of the patterned metal layer are exposed so as to form plural first contact pads for downward electrical connection externally. Afterwards, a second patterned dielectric layer is formed on the top surface of the patterned metal layer, and the second patterned dielectric layer at least exposes parts of the patterned metal layer to form plural second contact pads at the top surface of the patterned metal layer for upward electrical connection externally.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred but non-limiting embodiment. The following description is made with reference to the accompanying drawings.
In the present embodiment, a substrate having an embedded single patterned metal layer, and a package applying the substrate, and methods of manufacturing the substrate and package are disclosed. The substrate of the disclosure is related to a three-layered structure comprising a first patterned dielectric layer, a second patterned dielectric layer, and a patterned metal layer embedded in the first patterned dielectric layer. A top surface of the patterned metal layer is coplanar with a top surface of the first patterned dielectric layer, and at least part of the patterned metal layer are exposed from the first patterned dielectric layer so as to form plural first contact pads for downward electrical connection externally. The second patterned dielectric layer is formed above the patterned metal layer, and at least exposes part of the patterned metal layer to form plural second contact pads (ex: bonding pads) at the top surface of the patterned metal layer for upward electrical connection externally.
Compared to the prior art as depicted in
Several embodiments are provided to demonstrate the structures of substrate, and the package with the substrate, and methods of manufacturing the substrate and package. The methods of manufacturing the substrates would be slightly modified, without departing from the spirit of the invention, due to the different materials of the patterned base adopted in the embodiments. Also, the configurations of the substrates, material selections and the manufacturing processes described and illustrated in those embodiments are not intended to limit the invention. The modifications and variations can be made without departing from the spirit of the invention to meet the requirements of the practical applications.
Therefore, people skilled in the art would know that the structures and manufacturing methods presented in the embodiments and drawings could be slightly modified under the spirit of the invention. Also, it is also important to point out that the illustrations may not be necessarily be drawn to scale, and that there may be other embodiments of the present invention which are not specifically illustrated. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense. Additionally, the drawings used for illustrating the embodiments and applications of the present invention only show the major characteristic parts in order to avoid obscuring the present invention.
As shown in
As shown in
Afterwards, the first patterned dielectric layers 303 and 304 are formed on the bottom surfaces of the patterned metal layers 301 and 302, respectively. Also, there are several apertures 303a, 303b formed at the bottom surface of the first patterned dielectric layer 303 to expose parts of the bottom surface of the patterned metal layer 301, as shown in
Then, the transitional structures 41 and 42 formed so far are removed from the carrier 20, as shown in
Subsequently, the transitional structures 41 and 42 are removed from the carrier 20 and re-placed inversely on the carrier 20, so that the bottom surfaces of the first patterned dielectric layers 303 and 304 are respectively disposed on the carrier 20, as shown in
Then, the metal foils 201 and 202 are removed, as shown in
Afterwards, as shown in
Then, the structures formed so far are removed from the carrier 20, as shown in
With a suitable carrier 20, this can be done on both sides to allow double sided processing for increased efficiency. Take the substrate formed on the upper side of the carrier 20 (
In one embodiment, materials of the first patterned dielectric layers 303, 304 and the second patterned dielectric layers 305, 306 may be optionally selected from solder mask (SM), liquid crystal polymer (LCP), prepreg (PP), molding compounds, or other dielectric materials. Also, materials of the first patterned dielectric layers 303, 304 and the second patterned dielectric layers 305, 306 may be the same or different. The materials and selections of the first and second patterned dielectric layers 303-306 are not intended to be limited to these illustrative compounds.
Moreover, the substrate of
According to the above descriptions, the patterned metal layer 301 of the substrate, as shown in
Although
Besides substrate 51 of the first embodiment (
The method of fabricating the substrate 52 of
Similarly, the patterned metal layer 301 of the substrate, as shown in
Although two types of substrates 61, 62, and packages 71 and 72 have been illustrated with reference to specific embodiments, it is noted that the final structure of the substrate can be variable in accordance with requirements of the practical application. For example, the die could be wire bonded or flipped bonded to the substrate. Also, materials and patterns of the metal layer and dielectric layer would be varied from the illustration, depending to the specific requirements of the device. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention.
The foregoing description and illustrations contained herein demonstrate many of the advantages associated with the present embodiments over the prior art. By providing substrate having two patterned dielectric layers and a patterned metal layer, the thickness of the substrate is reduced to about 40 μm-130 μm giving rise to a lower profile package. This extra thin substrate is particularly suitable for the application of small-sized product. Also, the methods for manufacturing the substrates and packages disclosed in the foregoing embodiments are simple and suitable for mass production which has advantages of low cost and high yield of production. Compared to the prior art, the substrate structure of the disclosure satisfies the desired requirements of the electronic product with thin profile and low cost. Thus, the electronic product applied with the substrate of the present embodiment, especially for the small-sized and low-priced product, is very competitive in the commercial market.
While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Number | Date | Country | Kind |
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98125707 | Jul 2009 | TW | national |
This application claims the benefits of U.S. Provisional Application No. 61/177,652, filed May 13, 2009 and Taiwan Application No. 98125707, filed Jul. 30, 2009, the subject matter of which is incorporated herein by reference.
Number | Date | Country | |
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61177652 | May 2009 | US |