Patent Application
20070145607
Wirebond packages and flip-chip packages are commonly used to package one or more integrated circuit (IC) die. According to both types of packages, a lower surface of an IC die is coupled to an upper surface of an IC package substrate. A wirebond package includes wires to connect electrical contacts of a rear surface of the IC die to electrical contacts of the IC package substrate. In contrast, a flip-chip package includes electrical interconnects (e.g., solder bumps) to connect electrical contacts of a front surface of an inverted IC die to electrical contacts of the IC package substrate.
A wirebond package is typically less expensive than an equivalent flip-chip package. However, a wirebond package may not be suitable for some applications. An IC die used in a wirebond package requires a peripheral I/O ring that includes the above-mentioned electrical contacts. Accordingly, such an IC die will be larger than would be required if the IC die were intended for a flip-chip package. A wirebond package also delivers power to the periphery of an IC die. Such power delivery is less uniform than the power delivery of a flip-chip package, in which power is delivered more directly to a core of the IC die.
In may be desirable to selectively package an IC die in a wirebond package or a flip-chip package. Due at least to the above-described differences in power delivery and I/O routing, the design and fabrication of an IC die differs substantially depending on whether the IC die will be packaged in a wirebond package or a flip-chip package.
According to some embodiments, IC die 20 includes integrated electrical devices for providing microprocessor functionality and may be fabricated using any suitable materials and fabrication techniques. The electrical devices of IC die 20 may be electrically connected to conductive pillars 30 and/or conductive elements 40. The electrical devices may therefore also be connected to wires 50 via pillars 30 and elements 40. Wires 50 connected to conductive pillars 30 carry I/O signals and wires 50 connected to conductive elements 40 carry power or ground signals according to some embodiments.
In some embodiments, IC die 20 defines a plurality of inner apertures, and at least one of conductive elements 40 is disposed on two or more of the plurality of inner apertures and is electrically connected to an electrical conductor through the two or more inner apertures. IC die 20 may also define a plurality of peripheral apertures, with one of conductive pillars 30 being disposed on one of the plurality of peripheral apertures and electrically connected to a second electrical conductor through the peripheral aperture.
As shown, at least one of conductive elements 40 may be coupled to a central portion of grids 70. Conductive elements 40 may therefore provide delivery of power to a core of IC die 20 via a connected wire 50. Such an arrangement may exhibit a voltage drop that is smaller than a voltage drop exhibited by conventional arrangements in which power is delivered to the periphery of IC die 20 and grids 70. In this regard, conductive elements 40 may comprise copper having a thickness of 60 μm.
Two wires 50 are connected to each of illustrated pillars 30. These two wires are asymmetric according to some embodiments. Connecting two asymmetric wires to a pillar 30 may reduce a voltage drop between IC package substrate 60 and the pillar 30 in comparison to single-wire arrangements, and may also reduce crosstalk between the two wires.
IC die 20 includes conductor 21 and conductive traces 22. IC die 20 may also include vias, electrical devices, and conductive planes. Conductor 21 is disposed below peripheral aperture 23. As shown in
Conductive pillar 30 is electrically connected to conductor 21 through aperture 23. Accordingly, wire 50 is electrically connected to conductor 21. According to some embodiments, a conductive adhesion layer is deposited on conductor 23 prior to fabrication of pillar 30 thereon. The adhesion layer may comprise sputtered tin/copper.
Conductive element 40 is partially covered by oxide-resistant layer 32, and wires 50 are bonded to areas 44 of element 40 that are not covered by layer 32. As described with respect to conductive pillar 30, element 40 may comprise copper or any other conductive wire-bondable material, and layer 32 may comprise any suitable oxide-resistant layer for retarding growth of oxides on bonding areas 44. Conductive element 40 is ˜50 μm in height and layer 32 is ˜50 nm thick according to some embodiments.
Conductors 26 are disposed below inner apertures 25 and are electrically connected to conductive element 40 through apertures 25. Conductors 26 may or may not be connected to one another within IC die 20. In some embodiments, conductors 26 carry power or ground signals between wires 50 and power delivery grid 70. In this regard, one or all of conductors 26 may be connected to a core portion of grid 70. Such an arrangement may reduce a voltage drop between wires 50 and a core of IC 20 in comparison to conventional systems.
Initially, at 61, a conductive pillar is fabricated on a peripheral aperture of an IC die. Next, a conductive element is fabricated on two or more inner apertures of the IC die at 62. As described with respect to
The conductive pillar and the conductive element may be fabricated using any suitable techniques that are or become known. According to some embodiments, the conductive pillar and the conductive element are fabricated simultaneously using a copper electrodeposition process.
An oxide-resistant layer is deposited on the conductive pillar and the conductive element at 63. In some embodiments, the oxide-resistant layer is deposited using chemical vapor deposition and may comprise any suitable components. The layer may be deposited shortly after the elements and pillars are formed to retard the development of copper oxides thereon. The oxide-resistant layer may comprise a native oxide of the conductive pillar, in which case the layer may be “grown” at 63.
A first wire is bonded to the conductive pillar at 64. Bonding the first wire comprises establishing an electrical connection between the first wire and the conductive pillar.
Bonding head 70 also or alternatively vibrates at or near a resonant frequency of layer 32 to allow wire 50 to penetrate and fragment layer 32 as shown in
As shown, tool 120 has exposed bonding area 32A of pillar 30A. Device 100 then moves in the direction of the arrow to position head 110 over area 32A. Device 100 may subsequently move downward to bond wire 50 to area 32A and to expose a bonding area of pillar 30B.
Returning to process 60, a second wire is bonded to the conductive element at 65. The second wire may be bonded using any of the above-described techniques or any other suitable techniques. The second wire may be intended to carry power or ground signals to the conductive element. In some embodiments, more than one wire is bonded to a given conductive element as shown in
Many different layouts of conductive elements and/or copper pillars may be used in conjunction with some embodiments. Additionally or alternatively, embodiments may utilize many different wire bonding patterns.
Wires bonded to peripheral pillars 330 of apparatus 300 are to carry I/O signals, while wires bonded to conductive elements 340 carry power and ground signals. In the illustrated embodiment, the dashed lines represent wires carrying ground signals and the solid lines connected to conductive elements 340 represent wires carrying power signals. As shown, some wires are merely used to directly connect two conductive elements 340. Such wires may reduce a voltage drop exhibited by apparatus 300.
Apparatuses 400 and 500 of
Motherboard 620 may electrically couple memory 610 to apparatus 10. More particularly, motherboard 620 may comprise a memory bus (not shown) that is electrically coupled to solder balls 630 of apparatus 10 and to memory 610. Memory 610 may comprise any type of memory for storing data, such as a Single Data Rate Random Access Memory, a Double Data Rate Random Access Memory, or a Programmable Read Only Memory.
The several embodiments described herein are solely for the purpose of illustration. The various features described herein need not all be used together, and any one or more of those features may be incorporated in a single embodiment. Some embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.
