Patent Grant
9013035
1. Field of the Invention
The invention relates generally to the field of integrated circuit (IC) device packaging technology, and more particularly to the cooling of hotspots on IC semiconductor die, heat spreading for IC packages, and thermal interconnection technology in IC packaging.
2. Background Art
Electronic signals are carried by electrical current through conductors and transistors in a large scale integrated circuit (IC) fabricated on semiconductor substrate. The energy carried by the electrical current is partially dissipated along the paths of current flow through the IC in the form of heat. Heat generation in electronic semiconductor ICs is also known as power consumption, power dissipation, or heat dissipation. The heat generated, P, in an IC is the sum of dynamic power, PD, and static power, PS:
P=PD+PS=ACV2f+VIleak
where A is the gate activity factor, C is the total capacitance load of all gates, V is the peak-to-peak supply voltage swing, f is the frequency, and Ileak is the leakage current. The static power term, PS=VIleak, is the static power dissipated due to leakage current, Ileak. A further description regarding static power is provided in Kim et al, Leakage Current: Moore's Law Meets Static Power, IEEE Computer, 36(12): 68-75, December 2003, which is incorporated by reference herein in its entirety.
The dynamic power term, PD=ACV2f, is the dynamic power dissipated from charging and discharging the IC device capacitive loads. Dynamic power consumption is thus proportional to the operating frequency and the square of operating voltage. Static power consumption is proportional to the operating voltage. Advances in transistor gate size reduction in semiconductor IC technology have reduced the operating voltage and power dissipation for single transistors. However, on-chip power densities are expected continue to rise in future technologies as the industry continues to follow the trend set forth by Moore's Law. In 1965, Intel co-founder Gordon Moore predicted that the number of transistors on a chip doubles about every two years. In addition to the increased number of transistors on a chip, the operating frequencies also double about every two years according to the 2004 International Technology Roadmap for Semiconductors (ITRS Roadmap) (http://www.itrs.net/Common/2004Update/2004—00_Overview.pdf). Because of the increased difficulties in controlling noise margins as voltage decreases, operating voltages can no longer be reduced as quickly as in the past for 130 nm gate lengths and smaller. Consequently, on-chip power dissipation will continue to rise. See Table 6 of the ITRS Roadmap. With the increased use of 65 nm technology in foundry processes and the commercialization of 45 nm technology, power consumption is now a major technical problem facing the semiconductor industry.
Another characteristic of IC chips is the uneven distribution of temperature on a semiconductor die. More and more functional blocks are integrated in a single chip in system-on-chip (SOC) designs. Higher power density blocks create an uneven temperature distribution and lead to “hotspots,” also known as “hot blocks,” on the chip. Hotspots can lead to a temperature difference of about 5° C. to roughly 30° C. across a chip. Further description of hotspots is provided in Shakouri and Zhang, “On-Chip Solid-State Cooling For Integrated Circuits Using Thin-Film Microrefrigerators,” IEEE Transactions on Components and Packaging Technologies, Vol. 28, No. 1, March, 2005, pp. 65-69, which is incorporated by reference herein in its entirety.
Since carrier mobility is inversely proportional to temperature, the clock speed typically must be designed for the hottest spot on the chip. Consequently, thermal design is driven by the temperature of these on-chip hotspots. Also, if uniform carrier mobility is not achieved across the IC die due to on-chip temperature variations across the die, this may result in variations in signal speed and in complicating circuit timing control.
Heat spreaders, including drop-in heat spreaders, heat sinks, and heat pipes have been used in the past to enhance thermal performances of IC packages. Further descriptions of example heat spreaders are provided in U.S. Pat. No. 6,552,428, entitled “Semiconductor Package Having An Exposed Heat Spreader”, issued Apr. 22, 2003, which is incorporated by reference herein in its entirety. Further descriptions of example heat pipes are provided in Zhao and Avedisian, “Enhancing Forced Air Convection Heat Transfer From An Array Of Parallel Plate Fins Using A Heat Pipe, Int. J. Heat Mass Transfer, Vol. 40, No. 13, pp. 3135-3147 (1997).
For example,
Thermal enhancement methods, such as shown in
For example,
Active on-chip cooling methods that use electrical energy to remove heat from the IC chip are known in the art. For example, some have suggested pumping liquid coolant through micro-channels engraved in silicon to circulate on the semiconductor die and carry away waste heat. A further description regarding liquid cooling is provided in Bush, “Fluid Cooling Plugs Direct onto CMOS,” Electronic News, Jul. 20, 2005, http://www.reed-electronics.com/electronicnews/article/CA626959?nid=2019 &rid=550846255), which is incorporated by reference herein in its entirety. See also Singer, “Chip Heat Removal with Microfluidic Backside Cooling,” Electronic News, Jul. 20, 2005, which is incorporated by reference herein in its entirety.
Other active cooling methods have been developed in an attempt to provide active on-chip cooling using a thin-film thermoelectric cooler (TEC). A further description regarding on-chip cooling with TECs is provided in Snyder et al, “Hot Spot Cooling using Embedded Thermoelectric Coolers,” 22nd IEEE SEMI-THERM, Symposium, pp. 135-143 (2006), which is incorporated by reference herein in its entirety.
These active cooling methods require exotic and expensive fluid circulation or micro-refrigeration systems and add to the total power consumption of the package that must be removed. A separate power supply must also be integrated into the IC package to drive the fluid pumping or the TEC systems. These can be costly and can decrease component reliability. Because these solutions are typically expensive, their use is limited in cost sensitive applications such as consumer electronic devices.
These cooling methods as discussed above are inadequate and/or difficult and expensive to implement for commercial applications. What is needed is an inexpensive and reliable system and method of selective heat removal from hot blocks or hotspots on semiconductor dice.
Methods and apparatuses for improved integrated circuit (IC) packages are described herein.
In an aspect of the invention, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot on a surface of the IC die. A thermal interconnect member is attached to the hot spot. In an aspect of the invention, the package is encapsulated in a mold compound. In a further aspect of the invention, the die and thermal interconnect member are also electrically coupled.
In an aspect of the invention, the package also includes a heat spreader. The heat spreader may be thermally coupled to the thermal interconnect member. In a further aspect, the heat spreader is also electrically coupled to the thermal interconnect member. In an aspect of the invention, the heat spreader is completely encapsulated in mold compound. In another aspect, the heat spreader is at least partially exposed. In an aspect of the invention, the heat spreader has a plated area at a location corresponding to a location of the thermal interconnect member.
In an aspect of the invention, an integrated circuit (IC) package is manufactured by a method which includes attaching an IC die to a substrate, enabling electrical interconnection between the die and the substrate through a wire bonding process, coupling at least one thermal interconnect member to at least one contact pad on the die, and encapsulating the package in a mold compound or other encapsulating material. In another aspect of the invention, a portion of a thermal interconnect member (or a plurality of thermal interconnect members) is exposed. In an example aspect, an entire layer of mold compound is removed to expose the thermal interconnect member. In another example aspect, a cavity is carved into the mold compound to expose the thermal interconnect member.
In an aspect of the invention, the manufacturing method further includes coupling a heat spreader to the exposed thermal interconnect member. In an aspect, the heat spreader has plating at one or more location corresponding to the thermal interconnect member.
In another aspect of the invention, a die is analyzed to determine a location of at least one hotspot on a surface of the die that results from operation of the die. In an aspect, the analysis includes mapping functional blocks of the die to determine one or more hotspots. In another aspect, the analysis includes performing a thermal analysis of the die during operation to locate one or more hotspots.
In another aspect of the invention, a package includes a substrate having opposing first and second surfaces, an IC die mounted to the first surface of the substrate, a heat spreader, and a thermal interconnect member that couples the first surface of the substrate to a surface of the heat spreader.
These and other objects, advantages and features will become readily apparent in view of the following detailed description of the invention. Note that the Summary and Abstract sections may set forth one or more, but not all exemplary embodiments of the present invention as contemplated by the inventor(s).
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.
Embodiments of the present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.
Introduction
Methods, systems, and apparatuses for IC device packaging technology are described herein. In particular, methods, systems, and apparatuses for the (1) cooling of hotspots on IC semiconductor die, (2) heat spreading for IC packages, and (3) thermal interconnection technology in IC packaging are described.
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
The present specification discloses one or more embodiments that incorporate the features of the invention. The disclosed embodiment(s) merely exemplify the invention. The scope of the invention is not limited to the disclosed embodiment(s). The invention is defined by the claims appended hereto.
Furthermore, it should be understood that spatial descriptions (e.g., “above”, “below”, “left,” “right,” “up”, “down”, “top”, “bottom”, etc.) used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner.
Embodiments of the invention provide enhanced heat removal at desired locations on the surface of the semiconductor die. In conventional devices, entire IC die and/or IC package surfaces are cooled to keep the peak temperatures on the IC die below an operation threshold limit. In contrast, in an embodiment, one or more thermal interconnect members are coupled to one or more surfaces of an IC die. The thermal interconnect members remove heat from hot spots on the die. The thermal interconnect members provide one or more paths for heat transfer from the IC die through a mold that encapsulates the die to the outside environment.
In a further embodiment, the thermal interconnect members are coupled to a heat spreader. When the thermal interconnect members are coupled to a heat spreader integrated in the package, the thermal interconnect members function as thermal bridges through the mold that fills a gap between the die and heat spreader. Locations for the positioning the thermal interconnect members in contact with the die may be selected, by using an on-chip power density map and/or based on chip layout, for example.
In embodiments, one or more of the thermal interconnect members may be implemented with or without a heat spreader in all types of IC packages such as plastic ball grid array (PBGA), fine pitch ball grid array (BGA), land grid array (LGA), pin grid array (PGA), post-molded plastic leadframe packages such as quad flatpack (QFP) and no-lead quad flatpack (QFN) packages, and micro leadframe packages (MLP). For example, embodiments may be implemented in all wire-bond packages encapsulated with molded plastic to provide on-chip hot spot cooling as well as improving device overall heat dissipation capability.
Example Embodiments of Thermal Interconnect Members
In embodiments, thermal interconnect members are thermally conductive solder balls, solder bumps, posts, or other thermally conductive structures. In further embodiments, the thermal interconnect members are also electrically conductive. For the purposes of illustration, exemplary embodiments using a solder ball-based thermal interconnect structure are referred to below to explain the principles of the invention. However, embodiments may use other thermal interconnect structures. Thermal interconnect members may be made of a metal, such as gold, copper, aluminum, silver, nickel, or tin, may be made of a combination of metals/alloy, such as solder, a eutectic (tin, lead), a lead-free solder, may be made of a thermally conductive epoxy or other adhesive material, or may be made of other thermally conductive materials. In an embodiment, a thermal interconnect member is made of a core material that is coated with a bonding material such as solder, gold, silver, an epoxy, or other joining materials that mechanically bonds the thermal interconnect member with contact pads on a semiconductor die. In an embodiment, thermal interconnect members may be pre-deposited at pre-defined contact pads on a surface of the semiconductor die. In a further embodiment, one or more thermal interconnect members are also coupled to a heat spreader.
By attaching thermal interconnect members with a high power dissipation density to contact pads at areas on the die, which may be referred to as points or “blocks”, heat generated within these hotspots (also known as hot blocks) can be conducted away from the IC die directly to the external environment or through a thermally conductive heat spreader (if present) to the environment. In an embodiment, the placement of the one or more thermal interconnect members is based on a power map of a semiconductor die for a specific application. In another application, the same semiconductor die may have different on-chip thermal interconnect member locations if a different power maps results from the application. For example, this may occur when different functional blocks of the die switch from a “power-up” mode to a “power-down” mode, or vice versa, for different applications.
In an embodiment, a die is analyzed to determine a location of at least one hotspot on a surface of the die that results from operation of the die. In one embodiment, the analysis includes mapping functional blocks of the die to determine one or more hotspots. In another embodiment, the analysis includes performing a thermal analysis/measurement (e.g., as shown in
For example, some dies have peripheral bond pads (e.g., formed in one or more rings) at a surface of the die for internal I/O signals to be accessible externally from the die. First ends of wire bonds attach to the peripheral bond pads, and second ends of the wire bonds attach to the package substrate or other structures of the package. In embodiments, contact pads are attached to hotspots located in a central region of the surface of the die outside of the peripheral region of the wire bond pads, but in embodiments one or more contact pads may be located in a peripheral region of the surface of the die.
As shown in
In the embodiments of
For example, in an embodiment where thermal interconnect members 208 are solder balls, a junction-to-case thermal resistance is reduced because the thermal conductivity of typical (lead-free and tin/lead) IC package solder balls is around 50˜60 W/m*° C., which is many times higher than a typical mold compound 112, which may have a thermal conductivity of approximately 0.8 W/m*° C., for example. Furthermore, the solder balls forming thermal interconnect members 208 attached to IC die 102 extend the heat conduction area from the surface of die 102 to a top surface of mold compound 112. The thermal performance improvement is particularly significant for packages with a small size of die 102, when the solder balls displace a relatively large area of mold compound 112 on the top surface of die 102, providing a conductive path for heat dissipation through the top surface of package 250. Furthermore, when an external heat sink device, such as a heat sink or a metal plate, is attached to the top of a package such as packages 200 and 250, the thermal performance of the package may improve. Examples of such embodiments are described in detail below.
Example Embodiments of Packages with Attached Heat Spreaders
In embodiments, thermal interconnects facilitate on-chip power/heat dissipation from pre-selected locations on a semiconductor die. In an exemplary embodiment, at least one thermal interconnect is attached to an IC die and coupled to at least one heat spreader embedded or attached to the IC package. In an example embodiment, the heat spreader is encapsulated in a mold compound. The heat spreader may be exposed on a top surface of the package for heat dissipation to the ambient environment, including for attachment of a heat sink. The heat spreader can alternatively be entirely encapsulated within the mold compound of a molded IC package.
In embodiments, the heat spreader may have any of a variety of shapes and may include holes, slots, or other surface features for mold locking, heat dissipation, stress reduction, and/or improved reliability. The heat spreader may be made of metal such as copper, copper alloys, other materials typically used in leadframe packages (C151, C194, EFTEC-64T, C7025, etc.), aluminum, other metals or combinations of metals/alloy, and/or thermally conductive nonmetallic materials. The heat spreader may be a flexible tape substrate such as a polyimide tape substrate with one or more metal foil layers laminated on polyimide film. The heat spreader may be made of a thermally conductive but electrically non-conductive material, such as a thermally conductive ceramic, or it may also be electrically conductive.
In an embodiment, a distance between a bottom surface of an integrated heat spreader and a top surface of the die is less than a “loop-height” of the wire bond (i.e., a distance from the apex of the wire loop to the surface of IC die). In such an embodiment, a size of the heat spreader may be confined by a space between the wire bond pads on the opposite sides of the top surface of the IC die.
In another embodiment, the distance between the bottom of the heat spreader and the top of die is greater than the loop-height of wire bond. In this case, the size of the heat spreader is not limited by the distance between the bond pads on the opposite sides of the surface of the die. The size of the heat spreader may be greater than the size of the die, even if all four edges of surface of the die have wire bond interconnections. A larger heat spreader may deliver increased hotspot cooling due to a larger area for heat dissipation. To facilitate thermal connection, and reduce the gap between the IC die and the integrated heat spreader, a pedestal may be used that has an area less than an area of the die, and that extends towards the top surface of the IC die. Alternatively, thermal interconnects may be attached to the bottom of the heat spreader that can be thermally coupled with a corresponding thermal interconnect attached to the IC die.
In an embodiment, an integrated heat spreader is completely encapsulated by mold compound. In another embodiment, it is partially exposed through the mold top, such as in manner similar to drop-in heat spreader 104 shown in
In an embodiment where the thermal interconnects are electrically conductive, one or more thermal interconnects may be attached to the ground or power net of the IC die to provide an alternative route for current or on-chip power delivery from the heat spreader. Examples of such an arrangement are described in U.S. patent application Ser. No. 10/952,172, titled “Die Down Ball Grid Array Packages And Method For Making Same,” filed Sep. 29, 2004, which is incorporated herein by reference in its entirety. This may be effective in reducing the lengths of on-chip power supply current paths, thus reducing IR voltage drops within the IC die.
In an embodiment, the size of the heat spreader is less than a size of the package mold body, as illustrated in
In the following paragraphs, several exemplary embodiments of the invention are shown in various IC packages. The figures and descriptions are not intended to limit the invention, but merely illustrate the principles of the operation by example. Many of the examples described below include a heat spreader. However, as shown in
Example BGA Embodiments with Integrated Heat Spreader
For example,
In embodiments, heat spreader 302 may be partially or completely encapsulated by mold compound 112. Furthermore, although shown as planar in
Example PBGA Embodiments with Integrated Heat Spreader
In
Heat spreader 302 may be any regular or irregular shape, and planar or non-planar. For example,
Example Leadframe Embodiments with Integrated Heat Spreader
Embodiments of the invention can be implemented in many IC packages. For example,
Package 500 is encapsulated by mold compound 512, which fills a gap between heat spreader 502 and die 102, including cavity 520. A bottom surface of a perimeter rim portion 524 of heat spreader 502 is mounted to lead frame 516. As shown in
Note that although die-up configurations (i.e., circuit side of die 102 is facing away from the circuit board when mounted thereto) are shown in
In another embodiment, one or more thermal interconnect members 208 may be used in a leadframe package without an integrated heat spreader, in a similar manner as shown in
Example QFN Package Embodiments with Integrated Heat Spreader
Package 600 is encapsulated by mold compound 612, which fills a gap between heat spreader 602 and die 102, including cavity 620. A bottom surface of a perimeter rim portion 624 of heat spreader 602 is mounted to leads 616. As shown in
Example Embodiment of a Manufacturing Process for IC Packages: Encapsulate Before Attaching Optional Heat Spreader
Flowchart 700 begins with step 701. In step 701, a die is mounted to a substrate. For example, the die is die 102 shown in
In step 702, thermal interconnects are mounted on a top surface of the die. For example, one or more thermal interconnect members 208 are mounted on contact pads 202 on die 102, as shown in
In step 704, wire bonds are coupled between the die and substrate. For example, die 102 may be electrically connected to substrate 110 through a wire bonding process that attaches wire bonds 114.
In step 706, the package is encapsulated in mold compound. For example, the mold compound is mold compound 112. As shown in
In an optional step 708, a portion or all of a top layer of the mold compound is removed. For example, in an embodiment, a layer of mold compound 112 is removed such that one or more thermal interconnect members 208 are truncated (i.e., a top portion of thermal interconnect member 208 is removed along with a portion of the top layer, or the entire top layer of mold compound 112).
In optional step 708b, a cavity is formed in the mold compound.
In embodiments, other methods of material removal than those described above may be used in steps 708, 708a, and 708b to remove mold top material and expose and/or truncate one or more thermal interconnects. Other surface machining methods such as etching or laser machining may used to remove mold material and expose thermal/electrical interconnect elements.
As described above, step 708 (and sub-steps 708a and 708b) is optional. In an alternative embodiment, step 708 is not performed, and a layer and/or cavity of mold compound is not removed.
In optional step 710, a heat spreader is attached to the package. For example, the heat spreader is heat spreader 302, 502, 602, or 702, described above. In an embodiment of a package not having a heat spreader, optional step 710 is not performed. When step 710 is performed, the heat spreader is coupled to the one or more exposed thermal interconnects, which may or may not be truncated.
Note that the steps of flowchart 700 may be performed in orders other than shown in
Flowchart 800 begins in step 802. In step 802, a heat spreader having one or more pre-plated pads is received. For example, the heat spreader is heat spreader 302, as shown in
In step 804, the heat spreader is placed on the package. For example, as shown in
In step 806, the heat spreader is caused to become attached to the package. For example, to attach the heat spreader and package, a reflow or curing process may be conducted. The reflow or curing process causes heat spreader 302 to become attached to partially assembled package 860, to form package 870, as illustrated in
Example Embodiment of Manufacturing Processes for IC Packages: Encapsulate after Attaching Heat Spreader
Flowchart 900 begins with step 902. In step 902, a die is mounted to a substrate. For example, the die is die 102 of
In step 904, wire bonds are coupled between the die and the substrate. For example, as shown in
In step 906, thermal interconnects are mounted to a top surface of the die. For example, one or more thermal interconnect members 208 may be mounted to contact pads 202 on the top surface of die 102.
In step 908, the heat spreader is attached to the thermal interconnects. For example, as shown in
In step 910, the package is encapsulated in mold compound. For example, as shown in
Note that the steps of flowchart 900 may be performed in orders other than shown in
In a further embodiment, thermal interconnects may be attached to the heat spreader before being attached to the die.
Flowchart 950 begins with step 952. In step 952, a die is mounted to a substrate. For example, the die is die 102 of
In step 954, wire bonds are coupled between the die and the substrate. For example, as shown in
In step 956, thermal interconnects are mounted to a bottom surface of the heat spreader. For example, one or more thermal interconnect members 208 may be mounted to bottom surface 306 of heat spreader 302, as shown in
In step 958, the thermal interconnects are attached to the top surface of the die. For example, thermal interconnect members 208 are attached to die 102.
In step 960, the package is encapsulated in mold compound. For example, mold compound 112 is used to cover die 102, wire bonds 114, thermal interconnect members 208, and all or part of substrate 110.
Example Embodiments of Substrate Coupled Heat Spreader
In embodiments, thermal interconnect members may be used to couple a heat spreader to a substrate in an integrated circuit package. For example,
The packages of
Thermal interconnect member 208 may be coupled to top surface 1002 of substrate 110 at a non-electrically conductive location of substrate 110 and/or an electrically conductive location of substrate 110. For example, a bottom surface of thermal interconnect member 208 may be attached to a surface of a solder resist layer or dielectric layer of substrate 110, which are typically non-electrically conductive, and have a relatively low degree of thermal conductivity. In another example, the bottom surface of thermal interconnect member 208 may be attached to an electrically conductive feature 1004 of substrate 110, such as a trace, bond finger, contact pad, ground/power ring, etc., which are typically made of a metal (e.g., a metal foil, plating, etc) such as copper, aluminum, gold, tin, nickel, silver, another metal, or combination of metals/alloy.
In an embodiment where thermal interconnect member 208 couples electrically conductive feature 1004 of substrate 110 to heat spreader 302, thermal interconnect member 208 may provide an electrically conductive path to heat spreader 302 when thermal interconnect member 208 is electrically conductive.
As shown in
Any number of thermal interconnect members 208 may be present in embodiments to couple heat spreader 302 to substrate 110, including an array of thermal interconnect members 208. For example, in
In embodiments, flowcharts 700, 900, and 950, can be modified to include a step of forming/attaching thermal interconnects to a heat spreader and/or to a substrate to be used to couple the heat spreader to the substrate.
Note that although
Conclusion
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
This application claims the benefit of U.S. Provisional Appl. No. 60/814,876, filed Jun. 20, 2006, which is herein incorporated by reference in its entirety.
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| 1697169 | Nov 2005 | CN |
| WO03081669 | Oct 2003 | WO |
| WO 2005104314 | Nov 2005 | WO |
| Entry |
|---|
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| Bush, “Fluid Cooling Plugs Direct onto CMOS,” Electronic News, Jul. 20, 2005, http://www.reedelectronics.com/electronicnews/article/CA626959?nid=2019&rid=550846255). |
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| English Abstract of CN 1697169, publication date of Nov. 15, 2005. |
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| Number | Date | Country | |
|---|---|---|---|
| 20070290322 A1 | Dec 2007 | US |
| Number | Date | Country | |
|---|---|---|---|
| 60814876 | Jun 2006 | US |
